Power consumption reduction in medical devices employing...

Details Power consumption reduction in medical devices employing... Power consumption reduction in medical devices employing...

1999-07-22

2002-12-17

Evanisko, George R. (Department: 3762)

Surgery: light, thermal, and electrical application

Light, thermal, and electrical application

Electrical therapeutic systems

Reexamination Certificate

active

06496729

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to power consumption of integrated circuit designs such as circuits used in medical devices, particularly implantable devices. More particularly, the present invention pertains to providing adjustable clock control and/or multiple supply voltage levels for operation of such circuits.
BACKGROUND OF THE INVENTION
Various devices require operation with low power consumption. For example, hand-held communication devices require such low power consumption and, in particular, implantable medical devices require low power capabilities. With respect to implantable medical devices, for example, microprocessor-based implantable cardiac devices, such as implantable pacemakers and defibrillators, are required to operate with a lower power consumption to increase battery life and device longevity.
Generally, such low power devices are designed using complementary metal oxide semiconductor (CMOS) technology. CMOS technology is generally used because such technology has the characteristic of substantially zero “static” power consumption.
Power consumption of CMOS circuits consists generally of two power consumption factors, namely “dynamic” power consumption and static power consumption. Static power consumption is only due to current leakage as the quiescent current of such circuits is zero. Dynamic power consumption is the dominant factor of power consumption for CMOS technology. Dynamic power consumption is basically due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances. Dynamic power (P) is equal to: ½CV
DD
2
F, where C is nodal capacitance, F is the clock or switching frequency, and V
DD
is the supply voltage for the CMOS circuit. As can be seen from the formula for calculating dynamic power (P), such dynamic power consumption of CMOS circuits is proportional to the square of the supply voltage (V
DD
). In addition, dynamic power (P) is proportional to the switching or clock frequency (F).
In accordance with the formula for dynamic power consumption, it has been effective conventionally in CMOS integrated circuit designs to scale down the supply voltage for an entire device (e.g., hybrid) or integrated circuit (IC), i.e., operate the circuit at low supply voltages, to reduce power consumption for such designs. For example, in the MEDTRONIC SPECTRAX® product of circa 1979, IC circuitry was powered by one lithium iodine (as opposed to the two cells employed in the prior art). This reduced the supply voltage to 2.8 volts from 5.6 volts, thus reducing overhead current. Voltages required to be greater than 2.8 volts were generated by a voltage doubler, or alternatively by a charge pump (e.g., output pacing pulses). In the MEDTRONIC SYMBOLS® product of circa 1983, for example, logic circuitry was powered by a voltage regulator controlling the IC supply voltage to a “sum of thresholds” supply. This regulator provided a supply to the IC (i.e., V
DD
) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator was self calibrating regarding manufacturing variations of the transistor thresholds.
Other devices reduced power consumption in other manners. For example, various device designs have shut-down analog blocks and/or shut-off clocks to logic blocks not being used at particular times, thereby reducing power. Microprocessor based devices have historically used a “burst clock” design to operate a microprocessor at a very high clock rate (e.g., generally 500-1000 Kilohertz (KHz)), for relatively short periods of time to gain the benefit of a “duty cycle” to reduce average current drain. A much lower frequency clock (e.g., generally 32 KHz) is used for other circuitry and/or the processor when not in the high clock rate mode, i.e., burst clock mode. Many known processor based implanted devices utilize the burst clock technique. For example, implanted devices available from Medtronic, Vitatron, Biotroniç, ELA, Intermedics, Pacesetters, InControl, Cordis, CPI, etc., utilize burst clock techniques. A few illustrative examples which describe the use of a burst clock are provided in U.S. Pat. No. 4,561,442 to Vollmann et al., entitled “Implantable Cardiac Pacer With Discontinuous Microprocessor Programmable Anti Tachycardia Mechanisms and Patient Data Telemetry,” issued Dec. 31, 1985; U.S. Pat. No. 5,022,395 to Russie, entitled “Implantable Cardiac Device With Dual Clock Control of Microprocessor,” issued Jun. 11, 1991; U.S. Pat. No. 5,388,578 to Yomtov et al., entitled “Improved Electrode System For Use With An Implantable Cardiac Patient Monitor,” issued Feb. 14, 1995; and U.S. Pat. No. 5,154,170 to Bennett et al., entitled “Optimization for Rate Responsive Cardiac Pacemaker,” issued Oct. 13, 1992.
FIG. 1
illustrates graphically energy/delay versus supply voltage for CMOS circuits such as CMOS inverter
10
shown in
FIG. 2
for illustrative purposes. Inverter
10
is provided with a supply voltage, V
DD
, which is connected to the source of a PMOS field effect transistor (FET)
12
. PMOS FET
12
has its drain connected to the drain of a NMOS FET
14
whose source is connected to ground. In this configuration, an input V
i
applied to both the gates of FETs
12
,
14
is inverted to provide output V
o
. Simply stated, one clock cycle, or logic level change, is used to invert the input V
i
to V
o
.
As shown in
FIG. 1
, the circuit logic delay increases drastically as the supply voltage is reduced to near one volt, as represented by delay line
16
and energy/delay line
18
. As such, reducing of the supply voltage (V
DD
) continuously to lower levels is impractical because of the need for higher supply voltages when higher frequency operation is required. For example, generally CMOS logic circuits must periodically provide functionality at a higher frequency, e.g., burst clock frequency. However, as the supply voltage (V
DD
) is decreased, such energy consumption is reduced by the square of the supply voltage (V
DD
) as is shown by energy consumption line
20
. Therefore, speed requires a higher supply voltage (V
DD
) which is in direct conflict with low power consumption.
Other problems are also evident when lower supply voltages (V
DD
) are used for CMOS circuit designs. When a lower supply voltage is selected, static leakage current losses may arise, particularly at lower frequencies, due to increased static leakage current losses.
Various techniques for reducing power consumption in devices are known in the art, some examples of which may be found in the references listed in Table 1 below.
TABLE 1
Patent No.
Inventor
Issue Date
4,031,899
Renirie
June 28, 1977
4,460,835
Masuoka
July 17, 1984
4,561,442
Vollmann et al.
December 31, 1985
4,791,318
Lewis et al.
December 13, 1988
5,022,395
Russie
June 11, 1991
5,154,170
Bennett et al.
October 13, 1992
5,185,535
Farb et al.
February 9, 1993
5,388,578
Yomtov et al.
February 14, 1995
5,610,083
Chan et al.
March 11, 1997
All references listed in Table 1 herein above are hereby incorporated by reference in their respective entireties. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, Detailed Description of the Embodiments, and claims set forth below, at least some of the devices and methods disclosed in the present application, including those disclosed in the reference listed in Table 1 hereinabove, may be modified advantageously in accordance with the teachings of the present invention.
SUMMARY OF THE INVENTION
The present invention has certain objects. That is, various embodiments of the present invention provides solutions to one or more problems existing in the prior art respecting circuitry design having lower power consumption, particularly with respect to implantable medical devices. Those problems include: CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuits having too large of a dynamic power consumption which reduces battery life;

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