Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-03-16
2002-12-03
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000, C327S163000, C327S276000, C327S277000, C331S017000, C331S025000
Reexamination Certificate
active
06489823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and particularly to a synchronous semiconductor device taking in a signal in synchronization with an externally applied clock signal. More specifically, the present invention relates to an internal clock generation circuit in a synchronous dynamic random access memory (hereinafter referred to as an SDRAM) employing a delay-locked loop (hereinafter referred to as DLL) for an internal clock circuit.
2. Description of the Background Art
Dynamic random access memory (DRAM) used as main memory has been increased in speed. However, its operating speed still cannot catch up to that of microprocessors (MPUs). Thus it is often said that the DRAM's access time and cycle time become a bottleneck and the entire system is degraded in performance. In recent years, an SDRAM operating in synchronization with a clock signal is increasingly used as the main memory for a rapid MPU.
The SDRAM, synchronized with an external clock signal to takes in an external signal and data in a synchronous operation, is advantageous in that its data input/output time requires a smaller margin than conventional memory, which requires a margin for its data input/output time to consider a skewed (offset in timing) address signal.
As such, if as in an SDRAM an address signal and a data signal are synchronized by a clock signal and successive data can also be written and read, and shorter successive access times can be achieved.
As an MPU operates more and more rapidly, as has been described above, providing a more rapid internal clock signal for use internal to an SDRAM is an unavoidable issue in terms of the performance of the entire system as well as other aspects, since if an internal clock signal is slow an access time from a clock governs an operating frequency. As such, an SDRAM can have a delay-locked loop (DLL) receiving an external clock signal CLK and generating an internal clock signal ICLK synchronized with clock signal CLK.
FIG. 24
is a block diagram showing a configuration of a conventional DLL.
As shown in
FIG. 24
, an external clock signal CLK is fed to a clock buffer
502
which in turn outputs a signal ECLK. Signal CLK is fed to a DLL
510
. DLL
510
changes a phase of signal ECLK and outputs internal clock signal ICLK which is sent to an input/output buffer (not shown) receiving an address signal, a data signal and the like and serves as a clock for use in taking in an externally applied signal. Since internal clock signal ICLK can have its phase changed to be different than external clock signal CLK, for example a data signal can be timed differently in outputting data from the input/output buffer. If internal clock signal ICLK phase is set ahead of external clock signal CLK phase, a shorter access time can be achieved.
DLL
510
is of digital type. A DLL of digital type is considered suitable since in an SDRAM, which would suffer large power-supply noise, a DLL of analog type would result in large jitter or fluctuation attributed to the noise.
DLL
510
includes a delay line
522
delaying signal ECLK received from the clock buffer and outputting internal clock signal ICLK, a delay circuit
526
delaying internal clock signal ICLK for a period of time corresponding to a delay time to an internal circuit where internal clock signal ICLK is used, a phase comparator
528
comparing a phase of a signal RCLK output from delay circuit
526
and that of signal CLK with each other and outputting control signals UP and DOWN, and a shift register
524
responsive to an output from phase comparator
528
for controlling a delay time of delay line
522
. This DLL is a type of automatic control circuit.
When phase comparator
528
receives signals CLK and RCLK, phase comparator
528
compares the phases of the signals and outputs control signals UP and DOWN. When signals CLK and RCLK substantially match in phase, synchronization is established. The establishment of synchronization is generally referred to a DLL in locked state. Shift register
524
changes the delay time of the delay line in response to control signals UP and DOWN.
FIG. 25
is a circuit diagram showing one example of a configuration of delay line
522
shown in FIG.
24
.
As shown in
FIG. 25
, a shift register
524
feeds control signals C(
1
) to C(n) to delay line
522
.
Delay line
522
includes an NAND circuit
544
#
1
receiving signal ECLK and control signal C(
1
), an NAND circuit
546
#
1
having one input fixed to have a power supply potential VDD and the other input receiving an output of NAND circuit
544
#
1
, an inverter
547
#
1
receiving and inverting an output of NAND circuit
541
#
1
, an NAND circuit
544
#
2
receiving signals CLK and control signal C(
2
), an NAND circuit
546
#
2
receiving an output of NAND circuit
544
#
2
and an output of inverter
547
#
1
, and an inverter
547
#
2
receiving and inverting an output of NAND circuit
546
#
2
.
Delay line
522
also includes an NAND circuit
544
#n−1 receiving signal ECLK and control signal C (n−1), an NAND circuit
546
#n−1 receiving an output of inverter
547
#n−2 (not shown) and an output of NAND circuit
544
#n−1, an inverter
547
#n−1 receiving and inverting an output of NAND circuit
546
#n−1, an NAND circuit
544
#n receiving signal ECLK and control signal C(n), an NAND circuit
546
#n receiving an output of NAND circuit
544
#n and an output of inverter
547
#n−1, and an inverter
547
#n receiving and inverting an output of NAND circuit
546
#n and outputting internal clock signal ICLK.
Shift register
524
outputs control signals C(
1
) to C(n), of which only one signal is set high and the remaining signals are set low. For example, if control signal C(n−1) is driven high then signal ECLK is transmitted via NAND circuit
544
#n−1 and internal clock signal ICLK is responsively output. If a delay time is too long then the high level is output via a control signal shifted rightward in position and if a delay time is too short then the high level is output via a control signal shifted leftward in position. Thus a delay time is adjusted. In general, in powering on an SDRAM a minimal delay time is initially applied. As such, in
FIG. 25
, control signal C(n) is set high and via NAND circuit
544
#n signal ECLK is taken into the delay line.
If such a delay line is used, however, a delay time varies in a step corresponding to the sum-of a delay time of an NAND circuit and that of an inverter. For a high operating frequency, a conventional delay line, having a delay time varying in too large a step, can disadvantageously provide the delay time varying stepwise, resulting in no operating margin.
Furthermore, for a high operating frequency, locking a DLL requires a delay time shorter than the minimal delay. As such, the internal clock signal is limited in having high rate.
SUMMARY OF THE INVENTION
The present invention contemplates a semiconductor device incorporating an internal clock signal generation circuit allowing a delay time to vary in a small step to accommodate a clock signal of a high operating frequency.
The present invention provides a semiconductor device including a clock generation circuit and an internal circuit.
The internal clock signal generation circuit generates an operating clock signal in response to an external clock signal.
The internal clock generation circuit includes a phase comparator comparing a phase of the external clock signal and a phase of the operating clock signal with each other and a clock delay portion responsive to an output of the phase comparator for delaying a first internal clock signal to output an operating clock.
The clock delay portion has a clock conversion portion generating from the first internal clock signal a second internal signal and a third internal signal complementary to the second internal signal, and a clock output portion re
Callahan Timothy P.
Luu An T.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Semiconductor device capable of generating highly precise... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device capable of generating highly precise..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device capable of generating highly precise... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2986663