Debugging system for computer program, method for checking...

Details Debugging system for computer program, method for checking... Debugging system for computer program, method for checking...

1999-09-28

2002-10-15

Morse, Gregory (Department: 2122)

Data processing: software development, installation, and managem

Software program development tool

Testing or debugging

C711S156000, C712S227000, C714S047300

Reexamination Certificate

active

06467083

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a debugging technology and, more particularly, to a debugging system, a method for checking target programs to be executed by a data processor incorporated in a target system such as, for example, a facsimile and an image processing system and an information storage medium for storing a checking program.
DESCRIPTION OF THE RELATED ART
It is rare for a target program to be installed in a target system such as a facsimile and an image processing system to correctly run jobs upon completion of the development. Usually, a debugging system runs the target program, and traces the target program to see how the instructions are sequentially executed, how the execution changes the contents of registers and what data codes are left in the addressable memory locations in a main memory. The debugging system stores the results of the tracing operation in a trace memory as pieces of trace data information indicative of errors in the target program, and a programmer eliminates the bugs from the target program.
FIG. 1
illustrates a prior art debugging system disclosed in Japanese Patent Publication of Unexamined Application (laid-open) No. 1-201740. The prior art debugging system comprises a main memory
1
, a central processing unit
2
abbreviated as “CPU”, a read-only memory
3
abbreviated as “ROM”, a trace controller
4
and a trace memory controller
5
. An address bus and a data bus are shared between the main memory
1
, the central processing unit
2
, the read only memory
3
, the trace controller
4
and the trace memory controller
5
, and the main memory
1
, the central processing unit
2
, the read only memory
3
, the trace controller
4
and the trace memory controller
5
communicate with one another through the address/data buses.
The main memory
1
stores a target program to be checked, and the instruction codes of the target program are assigned addresses, respectively. The central processing unit
2
sequentially fetches instruction codes from the main memory
1
, and runs the target program so as to control component parts of the target system (not shown). While the central processing unit
2
is running the target program, the central processing unit
2
supplies an address data signal representative of the next address assigned to the instruction code to be executed to the trace controller
4
. The read-only memory
3
stores three kinds of address information as shown in FIG.
2
. The first kind of address information represents trigger addresses At/Bt/Ct/ . . . , the second kind of address information represents high-limit trace addresses Ah/Bh/Ch/ . . . , and the third kind of address information represents low-limit trace addresses Al/Bl/Cl/ . . . The read only memory
3
supplies address data signals respectively representative of the trigger address At/Bt/Ct/ . . . , the high-limit trace address Ah/Bh/Ch/ . . . and the low-limit trace address Al/Bl/Cl/ . . . to the trace controller
4
.
Turning back to
FIG. 1
of the drawings, the trace controller
4
includes a trigger address detector
6
, a high-limit trace address detector
7
, a low-limit trace address detector
8
and an AND gate
9
. The AND gate
9
is connected to the trace memory controller
5
, and supplies a trace enable signal thereto. The trace controller
4
instructs the trace memory controller
5
to start the tracing operation through the trace enable signal. The address data signal representative of the trigger address At/Bt/Ct/ . . . reaches the trigger address detector
6
, and the central processing unit
2
supplies the address data signal representative of the next address assigned to the instruction code to be executed to the trigger address detector
6
. The trigger address detector
6
determines a trigger point from the address data signals, and produces a trigger address detection signal representative of the trigger point to the read only memory
3
.
The address data signal representative of the high-limit trace address Ah/Bh/Ch/ . . . reaches the high-limit trace address detector
7
, and the central processing unit
2
further supplies the address data signal representative of the next address assigned to the instruction code to be executed to the high-limit trace address detector
7
. The high-limit trace address detector
7
checks the address data signals to see whether or not the next address exceeds the high-limit address. When the next address does not exceed the high-limit address, the high-limit trace address detector
7
changes a detecting signal to an active level, and supplies the detecting signal to the AND gate
9
. On the other hand, if the next address exceeds the high-limit address, the high-limit trace address detector
7
keeps the detecting signal inactive.
The address data signal representative of the high-limit trace address Al/Bl/Cl/ . . . reaches the low-limit trace address detector
8
, and the central processing unit
2
further supplies the address data signal representative of the next address to the low-limit trace address detector
8
. The low-limit trace address detector
8
checks the address data signals to see whether or not the next address reaches an address value less than that the low-limit address. When the next address falls within the address range defined by the high-limit address and the low-limit address, the low-limit trace address detector
8
changes a detecting signal to an active level, and supplies the detecting signal to the AND gate
9
. On the other hand, if the next address is lower than the low-limit address, the low-limit trace address detector
8
keeps the detecting signal inactive.
The detecting signals are supplied from the high-limit trace address detector
7
and the low-limit trace address detector
8
to the AND gate
9
. When both detecting signals are active, the AND gate
9
yields the trace enable signal of the active level, and supplies the trace enable signal to the trace memory controller
5
. With the trace enable signal of the active level, the trace memory controller
5
starts the tracing, and stores the pieces of trace data information in a built-in memory (not shown).
The prior art debugging system behaves as follows. The trigger address At is read out from the read only memory
3
, and is transferred to the trigger address detector
6
. The high-limit trace address Ah is further read out from the read only memory
3
, and is transferred to the high-limit trace address detector
7
. The low-limit trace address Al is further read out from the read only memory
3
, and is transferred to the low-limit trace address detector
8
. Thus, the trigger address At, the high-limit trace address Ah and the low-limit trace address Al are stored in the trigger address detector
6
, the high-limit trace address detector
7
and the low-limit trace address detector
8
, respectively.
Subsequently, the central processing unit
2
sequentially fetches the instruction codes of the target program, and executes them. Various control signals are produced through the execution, and the component parts of the target system (not shown) are controlled with the control signals. While the central processing unit
2
is running the target program, the central processing unit
2
produces the address data signal representative of the next address assigned to the instruction code presently executed and data signals supplied to the target system. The address data signal is supplied through the address bus to the main memory
1
and the data signals to the target system. The central processing unit
2
further supplies the address data signal to the trigger address detector
6
, the high-limit trace address detector
7
and the low-limit trace address detector
8
. The high-limit trace address detector
7
and the low-limit trace address detector
8
respectively compare the next address with the high-limit trace address and the low-limit trace address to see whether or not the next address falls within the address range defined by the high-limit trace address and the low-limit trace a

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