Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-03-06
2002-10-22
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000, C341S120000, C341S143000, C341S157000
Reexamination Certificate
active
06469650
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to an analog-to-digital converter, and, in particular, to a filter controller for an analog-to-digital (“A/D”) converter. Still more particularly, the present invention relates to a method and system for selecting implementation of a filter controller for an analog-to-digital converter between a single conversion mode that ensures a fully-settled converted output and a continuous conversion mode.
2. Description of the Related Art
Analog-to-digital converters (“ADCs”) are used to convert an analog signal to a digital signal for digital processing and/or storage. ADCs are well known in the art and are used in a variety of applications. An ADC generally has an analog system and a digital system coupled to each other. The analog system includes at least a modulator for modulating the input analog signal. The analog system processes and converts an analog input signal to a digital output signal. The digital system processes and outputs the digital signal. The digital system has at least a filter. The filter operates to remove and/or reduce unwanted parts of the digital signal. The filter also extracts the important information by using digital signal processing (“DSP”) techniques. The filter may further control the mode in which the digitized bit stream from the analog system is to be converted. Two exemplary modes of conversion performed on a signal are the single conversion mode and the continuous conversion mode.
Applications of the ADC that take only a single sample or reading (e.g., single temperature or weight reading) would require the ADC to operate in the single conversion mode. In the single conversion mode, the analog system digitizes an input signal and continuously outputs digitized bits of data as a bit stream. The filter then receives the bit stream from the analog system. The filter then filters only a single set of bits from the bit stream and converts the single set of bit along with a remaining number of bit sets, which may have non-updated values or initial zero values, into a conversion word. A predetermined number of bit sets are required for an accurate (or fully-settled) conversion word. However, only a single bit set has been converted, resulting in an inaccurate conversion word. A latency associated with the conversion therefore exists. In the single conversion mode, the filter disregards latter bit sets provided by the analog system after the filter outputs the conversion word. Furthermore, applications of the ADC that take only continuous samples or readings (e.g., continuous monitoring of temperature or weight readings) would require the ADC to operate in the continuous conversion mode. In the continuous conversion mode, the analog system also digitizes an input signal and continuously outputs digitized bits of data as a bit stream. The filter then receives the bit sets, filters, and converts the bit sets and then outputs the conversion word continuously. In the continuous conversion mode, the ADC continuously outputs conversion words so long as the filter receives bit sets to convert into conversion words.
Signals that are input into and flowing through an ADC for processing may take time to settle in the ADC circuitry. In other words, latency associated with conversions may exist. One problem that currently exists with the single conversion mode is that the conversion word outputted by the filter does not represent a fully-settled conversion word due to the latency associated with the filter. This problem of a non-fully-settled conversion word occurs when a conversion word is output by the filter before all the required sets of bits for a fully-settled conversion output have been sampled and provided by the analog system. The accuracy and performance of the ADC is significantly affected when the ADC is operating in the single conversion mode and the filter does not take the various bit sets needed for a fully-settled conversion word.
Another problem exists with the ADC chip in that typically an extra pin, such as a conversion mode pin, needs to be made part of the chip in order to switch between operating the ADC in the single conversion mode and the continuous conversion mode. For example, if the conversion mode pin is set high or to a one value, then the ADC chip operates in the continuous conversion mode. Alternatively, if the conversion mode pin is set low or to a zero value, then the ADC chip operates in the single conversion mode. The addition of an extra pin on the ADC circuit adds to the size and cost of the ADC chip.
The present invention recognizes the need for an ADC when operating in the single conversion mode that ensures a fully-settled converted output. Furthermore, the present invention recognizes the need to enable switching between the single conversion mode and the continuous conversion mode but at the same time recognizes the need to reduce pins on an ADC circuitry, which minimizes or reduces cost of the overall ADC chip. The present invention overcomes the problems and disadvantages in accordance with the prior art.
SUMMARY OF THE INVENTION
A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. The filter controller controls a filter in a digital system of an analog-to-digital converter. The filter controller has a state machine for implementing the selection. The state machine detects a convert start signal, which signifies a start of a conversion process. The state machine determines whether the convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. The conversion done is an occurrence of when a bit set has been converted from the input signal. If the convert start signal has a duration which ends on or before the first occurrence of the conversion done, then the state machine selects and implements the single conversion of the input signal. The digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, the state machine selects and implements the continuous conversion of the input signal.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5886658 (1999-03-01), Amar et al.
Amar Aryesh
Johnston Jerome E.
Nanda Kartik
Wong Saibun
Cirrus Logic Inc.
Lin, Esq. Steven
Nguyen Linh Van
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