Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-07-01
2002-12-10
Le, Vu A. (Department: 2784)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185280
Reexamination Certificate
active
06493270
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory devices, and more particularly, to leakage detection in a programming algorithm for a flash memory device.
BACKGROUND
Electrically erasable and programmable read-only memory devices having arrays of what are known as flash cells, also called flash EEPROMs or flash memory devices, are found in a wide variety of electrical devices. A flash memory device is typically formed in an integrated circuit. A conventional flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain in a substrate and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is separated from the channel region by a layer of gate oxide, and an inter-poly dielectric layer separates the control gate from the floating gate. Both the control gate and the floating gate are formed of doped polysilicon. The floating gate is floating or electrically isolated. The flash memory device has a large number of flash cells in an array where the control gate of each flash cell is connected to a word line and the drain is connected to a bit line, the flash cells being arranged in a grid of word lines and bit lines.
A flash cell is programmed by applying approximately 10 volts to the control gate, between 5 and 7 volts to the drain, and grounding the source and the substrate to induce hot electron injection from the channel region to the floating gate through the gate oxide. The voltage at the control gate determines the amount of charge residing on the floating gate after programming. The charge affects current in the channel region by determining the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As the charge on the floating gate increases the threshold voltage increases.
One type of flash memory device includes an array of multi-bit or multi-state flash cells. Multi-state flash cells have the same structure as ordinary flash cells and are capable of storing multiple bits of data in a single cell. A multi-bit or multi-state flash cell has multiple distinct threshold voltage levels over a voltage range. Each distinct threshold voltage level corresponds to a set of data bits, with the number of bits representing the amount of data which can be stored in the multi-state flash cell.
Data is stored in conventional flash memory devices by programming flash cells that have been previously erased. A flash cell is erased by applying approximately −10 volts to the control gate, 5 volts to the source, grounding the substrate and allowing the drain to float. In an alternate method of erasure the control gate is grounded and 12 volts is applied to the source. The electrons in the floating gate are induced to pass through the gate oxide to the source by Fowler-Nordheim tunneling such that the charge in the floating gate is reduced and the threshold voltage of the flash cell is reduced. Flash cells in an array in a flash memory device are grouped into blocks, and the cells in each block are erased together.
A flash cell is read by applying approximately 5 volts to the control gate, approximately 1 volt to the drain, and grounding the source and the substrate. The flash cell is rendered conductive and current in the cell is sensed to determine data stored in the flash cell. The current is converted to a voltage that is compared with one or more reference voltages in a sense amplifier to determine the state of the flash cell. The current drawn by a flash cell being read depends on the amount of charge stored in the floating gate.
The capacity of flash memory devices to store data is gradually being increased by reducing the size and increasing the number of flash cells in each integrated circuit. The reduction in the size of the flash cells renders them more vulnerable to leakage. Leakage is an unwanted loss of charge from the floating gate of a flash cell and may occur for one of several reasons. Data retention may deteriorate as charge slowly drifts out of the floating gate over the 10 to 100 year operating life of the flash memory device. Environmental conditions in which the flash memory device operates, such as temperature, may influence the leakage. The leakage may also occur when the flash cell is disturbed in the following manner. When a flash cell is being programmed, erased, or read, its word line, or bit line, or both, may be coupled to a voltage that is elevated in either a positive or negative direction. Adjacent flash cells sharing the same word line or bit line will also receive the elevated voltage which can disturb voltage differentials between the control gates, drains, and sources of the adjacent flash cells. The disturbance may cause charge to leak from the floating gates of some of the adjacent flash cells. Depending on the array structure multiple cycles of programming or an erase of flash cells in a block could induce leakage in cells in different blocks in the array. If sufficient leakage occurs in a programmed flash cell over its lifetime it may gradually move to a state in which a read operation will indicate that it is erased. This is called a bit failure. As flash cells get smaller and more flash cells are placed in a given area of a silicon chip there is an increased tendency for a flash cell to be disturbed and to suffer leakage.
Accordingly, there exists a need for a method of identifying flash cells that are leaky.
SUMMARY OF THE INVENTION
The above mentioned and other deficiencies are addressed in the following detailed description. According to one embodiment of the present invention a method includes programming a first flash cell in an array of flash cells in a flash memory device, sequentially selecting flash cells connected to the first flash cell, testing each selected flash cell to determine if the selected flash cell is leaky, and applying a refresh pulse to the selected flash cell if the selected flash cell is leaky. According to another embodiment of the present invention a flash memory device includes an array of flash cells, a program circuit to apply a programming pulse to program a first flash cell in the array, and a control circuit including elements to sequentially select flash cells connected to the first flash cell, test each selected flash cell to determine if the selected flash cell is leaky, and cause the program circuit to apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
Advantages of the present invention will be apparent to one skilled in the art upon an examination of the detailed description.
REFERENCES:
patent: 5317535 (1994-05-01), Talreja et al.
patent: 5434815 (1995-07-01), Smarandoiu et al.
patent: 5617350 (1997-04-01), Roohparvar et al.
patent: 5715193 (1998-02-01), Norman
patent: 6052321 (2000-04-01), Roohparvar
patent: 6108241 (2000-08-01), Chevallier
Le Vu A.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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