Patent
1978-03-07
1981-05-05
Wojciechowicz, Edward J.
357 23, 357 34, 357 36, 357 41, 357 43, 357 46, 357 50, 357 58, H01L 2704
Patent
active
042662389
ABSTRACT:
An improved transistor comprising an embedded electrode formed in a semiconductor substrate and having a high resistivity semiconductor region intervening between the embedded electrode and the substrate. The dimension and the impurity concentration of the high resistivity region are selected to insure that this latter region is substantially pinched off in the operative state of this transistor by the depletion layer growing from either the embedded electrode or the substrate, the width of said depletion layer varying in good faith without delay with the quick changes in the voltage of the embedded electrode. This provides an effective reduction mainly in the capacitance between the embedded electrode and the substrate, and also in the conductance in high-speed operation, which jointly bring about a high speed operation and a large driving ability. This transistor is extremely useful when adopted in a semiconductor integrated circuit.
REFERENCES:
IEEE-vol. Ed.-22, No. 4, Apr. 1975, Nishizawa et al.
Wojciechowicz Edward J.
Zaidan Hojin Handotai Kenkyu Shinkokai
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