Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2000-09-20
2002-10-29
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S072000, C257S098000
Reexamination Certificate
active
06472698
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a structure and a fabricating method of a solid state image sensor having micro lenses.
A conventional solid state image sensor of the type having a transfer layer for transferring a signal charge obtained by a photo-electric conversion, is generally classified into a MOS type and a CCD type. This solid state image sensor, particularly the CCD type solid state image sensor is recently widely used in a single-unit video-camera recorder, a digital camera, a facsimile, etc., and, at present, technology development is still continuously attempted for elevating the characteristics.
The CCD type solid state image sensor includes a photoelectric conversion section, namely, an image sensor section, which is constituted by arranging in a two-dimensional array a number of photoelectric conversion elements corresponding to pixels. Signal charges obtained in the photoelectric conversion section are read out in order through a vertically transferring CCD and a horizontally transferring CCD, so that a signal of each pixel is read out sequentially.
On the other hand, a CMOS type solid state image sensor does not utilize a CCD for the vertical transfer and the horizontal transfer, but is configured to read from a selected pixel through a selection line formed of an aluminum interconnection as in a memory device.
Furthermore, the CCD type solid state image sensor needs a plurality of power supply voltages including a positive power supply voltage and a negative power supply voltage, but the CMOS type solid state image sensor can be driven with a single power supply voltage, and therefore, can be operated with a power consumption and a power voltage which are lower than those required in the CCD type solid state image sensor.
In addition, since the CCD type solid state image sensor is fabricated with an inherent fabricating process, it is difficult to apply a CMOS circuit fabricating process with no modification. On the other hand, since the CMOS type solid state image sensor can be fabricated with the CMOS circuit fabricating process, it can be formed simultaneously together with a logic circuit, an analog circuit, an analog-to-digital converting circuit and others, by means of a CMOS process which is widely used in a processor, a semiconductor memory such as a DRAM, and a logic circuit. Accordingly, the CMOS type solid state image sensor can be formed together with the semiconductor memory and the processor on the same semiconductor chip, and can be fabricated in a production line in common to the semiconductor memory and the processor.
A conventional basic cell in an image sensor section and a portion of a logic circuit section in the above mentioned CMOS type solid state image sensor will be now shown in
FIG. 4B
as a first prior art example.
Referring to
FIG. 4B
, the reference number
1
designates a P-type silicon substrate, and the reference number
2
indicates a first P-well in the image sensor section. The reference number
3
denotes a second P-well in a CMOS circuit section, and the reference number
4
shows an N-well in the CMOS circuit section. The reference number
5
designates an N-type diffused layer which constitutes a photodiode in the image sensor section, and the reference number
6
indicates a P+ diffused layer. The reference number
7
denotes an N+ diffused layer, and the reference number
8
shows a gate electrode. The reference number
9
designates a first level metal interconnection, and the reference number
10
indicates a second level metal interconnection. The reference number
13
denotes an insulating film, and the reference number
31
shows a third level metal interconnection constituting a light block film having an opening through which an incident light passes. The reference number
43
designates an insulating film, and the reference number
34
indicates a planarizing layer formed of a transparent resin. The reference number
35
denotes a micro lens
35
.
The basic cell in the image sensor section of the CMOS type solid state image sensor is illustrated in
FIGS. 6A and 6B
. In
FIGS. 6A and 6B
, the reference number
51
designates a controlling MOSFET, and the reference number
52
indicates a MOSFET of a source follower amplifier. The reference number
53
denotes a horizontal selection switch MOSFET, and the reference number
54
shows a load MOSFET of the source follower amplifier. Elements designated with the same references numbers as those used in
FIG. 4B
corresponds to those given with the same reference numbers in FIG.
4
B.
The CMOS type solid state image sensor having the above mentioned structure operates as follows:
First, as shown in
FIG. 6A
, a pulse &phgr;R of a high level is applied to a gate of the controlling MOSFET
51
, so that a potential of the N-type diffused layer
5
constituting the photodiode of the image sensor section is set to a power supply voltage V
DD
, whereby a signal charge in the N-type diffused layer
5
is reset.
Then, as shown in
FIG. 6B
, the pulse &phgr;R of a low level is applied to the gate of the controlling MOSFET
51
, in order to prevent a blooming.
In the process of a signal charge accumulation, if electron-hole pairs are generated in a region under the N-type diffused layer
5
(constituting the photodiode of the image sensor section) in response to an incident light, electrons are accumulated in a depletion layer of the N-type diffused layer
5
, and on the other hand, the holes are exhausted through the first P-well
2
. Here, a region hatched with a grill-work pattern in
FIG. 6B
, having a potential deeper than the power supply voltage V
DD
, indicates that the region does not become the depletion layer. Between the depletion layer formed in the first P-well
2
under the N-type diffused layer
5
and the N+ diffused layer
7
applied with the power supply voltage V
DD
, a potential barrier is created by the controlling MOSFET
51
, so that the electrons are accumulated under the N-type diffused layer
5
in the process of the signal charge accumulation as shown in FIG.
6
B.
Succeedingly, the potential of the N-type diffused layer
5
varies upon the number of the accumulated electrons. This potential variation is outputted to a drain of the horizontal selection switch MOSFET
53
through the MOSFET
52
of the source follower amplifier in a source follower operation, and finally is outputted from an output terminal V
OUT
of the source follower amplifier. Thus, a photoelectric conversion characteristics having an excellent linearity can be obtained.
Now, a method for fabricating the above mentioned CMOS type solid state image sensor will be described with reference to
FIGS. 3A
,
3
B,
4
A and
4
B.
First, the first P-well
2
, the second P-well
3
and the N-well
4
are selectively formed on a principal surface of the P-type silicon substrate
1
.
Succeedingly, the N-type diffused layer
5
(constituting the photodiode of the image sensor section), the P+ diffused layer
6
, the N+ diffused layer
7
and the gate electrode
8
are formed as shown, by means of well-known photolithography, dry-etching and ion implantation.
Then, the first metal interconnection
9
and the second metal interconnection
10
(for supplying a pulse or a voltage or for outputting a signal to or from the N-type diffused layer
5
(constituting the photodiode of the image sensor section), the P+ diffused layer
6
, the N+ diffused layer
7
and the gate electrode
8
) are formed through the insulating film
13
. Furthermore, the third metal interconnection
31
(constituting the light blocking film having the opening above the N-type diffused layer
5
, and a bonding pad
36
) is formed. In the shown example, the third metal interconnection
31
constituting the light blocking film is formed as an uppermost level interconnection, but the position of the third metal interconnection
31
is not limited to only this level. For example, the third metal interconnection
31
can be formed on a lower level interlayer ins
Abraham Fetsum
McGinn & Gibb PLLC
NEC Corporation
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