Semiconductor memory integrated circuit having high-speed...

Details Semiconductor memory integrated circuit having high-speed... Semiconductor memory integrated circuit having high-speed...

2001-09-26

2002-11-05

Mai, Son (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S072000

Reexamination Certificate

active

06477074

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2000-370482, filed on Dec. 5, 2000, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, in particular, suitably used for reading and writing data using a read amplifier and a write buffer, such as DRAM.
2. Description of the Related Art
FIGS. 9A and 9B
show the conventional configuration of a DRAM as a representative example of semiconductor memory. As shown in
FIG. 9A
, the DRAM
1
of one chip is divided into four banks (Bank
0
to Bank
3
). Each of the banks is further divided into segments
3
by segment row decoder strings
2
. Pads
4
are provided in each peripheral circuit disposed between the banks.
FIG. 9B
shows the construction of one segment
3
sandwiched by two segment row decoder strings
2
. The segment
3
includes memory cell arrays
5
with memory cells, and sense amplifier strings
6
disposed adjacent to the memory cell arrays
5
and each made up from sense amplifiers. The sense amplifiers in the sense amplifier strings
6
are disposed to correspond to the respective memory cells in the memory cell arrays
5
.
The segment
3
further includes read amplifier circuits (R/A)
7
and write buffer circuits (W/B)
8
to correspond to units of data DQ. The read amplifier circuits
7
and the write buffer circuits
8
are so arranged as to be alternately adjacent to the corresponding data DQ. Each read amplifier circuit
7
and each write buffer circuit
8
are connected to a read global data bus rgdb_t/c and a write global data bus wgdb_t/c, respectively, which run in a segment direction (row direction). These global data buses rgdb_t/c and wgdb_t/c are connected to a read local data bus rldb_t/c and a write local data bus wldb_t/c, respectively, which run in a sense amplifier string direction (column direction).
Furthermore, first circuits
9
for controlling and driving a local write selection signal lwsel_p are arranged in cross portions (SS-Cross) of the segment row decoder strings
2
and the sense amplifier strings
6
. Also, second circuits
10
for controlling and driving a global write selection signal gwsel_p and a write buffer enable signal wep_p are arranged in cross portions of the segment row decoder strings
2
and an amplifier string
17
.
In data read, data read out from a predetermined memory cell in the memory cell array
5
is sensed by the corresponding sense amplifier. This data is supplied to the read amplifier
7
via the read local data bus rldb_t/c and the read global data bus rgdb_t/c. The data is then output to the outside through an output circuit (not shown) and the pad
4
.
In data write, data input through the pad
4
is supplied to the write buffer
8
via an input circuit (not shown). This write buffer
8
is activated when the write buffer enable signal wep_p supplied from the second circuit
10
is activated. The output signal of the write buffer
8
is supplied to the sense amplifier corresponding to a memory cell, to which data write is to be performed, via the write global data bus wgdb_t/c and the write local data bus wldb_t/c. The data sensed by this sense amplifier is written in the corresponding memory cell.
In this conventional semiconductor memory as shown in
FIGS. 9A and 9B
, in each segment
3
, the read amplifiers
7
and the write buffers
8
are disposed adjacent to the corresponding data DQ, so that these read amplifiers
7
and write buffers
8
are alternately arranged.
In this conventional art, however, the read amplifiers
7
are dispersed in the amplifier string
17
in the segment
3
. Therefore, if data read out from a memory cell by activating the sense amplifier closest to the segment row decoder of the segment
3
is to be amplified by the read amplifier
7
closest to the segment row decoder on the opposite side of the segment
3
through the read local data bus rldb_t/c and the read global data bus rgdb_t/c, the read data path from the sense amplifier to the read amplifier
7
is long (FIG.
10
A). Consequently, the influence by the wiring resistance may delay the read operation.
Likewise, when write data driven by the write buffer
8
closest to the segment row decoder of the segment
3
is to be supplied to the activated sense amplifier closest to the segment row decoder on the opposite side of the segment
3
through the write global data bus wgdb_t/c and the write local data bus wldb_t/c and written in the corresponding memory cell, the write data path from the write buffer
8
to the sense amplifier is long (FIG.
10
B). As a consequence, the influence by the wiring resistance may delay the write operation.
Also, the wiring layouts of control signals for write operations are as follows. Lines for the global write selection signal gwsel_p which is driven from the second circuits
10
to the first circuits
9
can be easily formed. However, the write buffer enable signal wep_p similarly driven from the second circuits
10
is driven long distances to the write buffers
8
dispersed in the amplifier string. In addition, the read amplifiers
7
exist between the write buffers
8
. Hence, lines for this signal are difficult to form. That is, the consistency between lines connecting the circuits for write operations is low.
Data read and write operations in a semiconductor memory are important operations in relation to the performance of the memory. Accordingly, it is desirable to rapidly perform these read and write operations.
SUMMARY OF THE INVENTION
It is the first object of the present invention to realize high-speed data read and write operations by reducing the wiring load on data paths in data read and write operations.
It is the second object of the present invention to improve the consistency between lines connecting circuits for write operations.
In a semiconductor memory of the present invention, at least one of read amplifier circuits for amplifying read-out data transferred from a sense amplifier and write buffer circuits for driving write data to the sense amplifier are arranged adjacent to each other.
For example, the distance of a read data path can be shortened by arranging read amplifier circuits adjacent to each other. Also, the distance of a write data path can be shortened by arranging write buffer circuits adjacent to each other.
Furthermore, write buffer circuits are dispersed on both sides of read amplifier circuits arranged adjacent to each other, and a second circuit for controlling and driving a global write selection signal and a write buffer enable signal is disposed at or in the vicinity of a cross portion of a segment row decoder string and an amplifier string. Since the circuits for write operations can be gathered near the segment row decoder string, a wiring layout having high consistency can be formed.


REFERENCES:
patent: 5615166 (1997-03-01), Machida
patent: 5724281 (1998-03-01), Nagaba

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