Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-06-26
2002-12-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06492848
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a power-on reset circuit to produce a stable reset signal irrespective of driving speed of a power-on signal which is applied thereto at the time of its initial chip operation.
DESCRIPTION OF THE PRIOR ARTS
Generally, in case where a reset signal for initializing a chip is inputted through an external pin, an additional pin makes the chip go up in price. Accordingly, instead of using an additional reset pin, a circuit to generate a reset signal automatically, whenever the power is inputted into the chip, should be included in the chip itself. This circuit is called a power-on reset circuit.
FIG. 1
is a block diagram illustrating a conventional power-on reset circuit. As shown in
FIG. 1
, the conventional power-on reset circuit includes an input unit
110
receiving a power-on signal and outputting toggled pulse signals and a schmitt trigger
130
outputting a power-on reset signal in response to an output signal from the input unit
110
.
The input unit
110
includes a capacitor C
11
between an input pad of the power-on signal and node N
11
, an NMOS transistor NM
11
which has a gate connected to node N
11
, a drain connected to node N
11
and a source connected to a ground voltage level, a PMOS transistor PM
11
which has a gate connected to node N
11
, a source connected to the input pad of the power-on signal and a drain connected to an output node N
12
, and a capacitor C
12
coupled between the output node N
12
and the ground voltage level.
The schmitt trigger
130
includes a schmitt trigger inverter
131
and an inverter INV
11
. Two PMOS transistors PM
13
and PM
14
are in series connected to each other and also two NMOS transistors NM
13
and NM
14
are in series connected to each other. Gates of these transistors PM
13
, PM
14
, NM
13
and NM
14
are coupled to the output node N
12
. A source of the PMOS transistor PM
13
is connected to the input pad of the power-on signal and a drain of the PMOS transistor PM
14
is connected to node N
13
. Accordingly, the power-on signal is transferred to node N
13
in response to a voltage level at node N
12
. Also, a drain of the NMOS transistor NM
13
is connected to the drain of the PMOS transistor PM
14
and the source of the NMOS transistor NM
14
is connected to the ground voltage level. A PMOS transistor PM
15
in the schmitt trigger inverter
131
is coupled between the ground voltage level and a drain of the PMOS transistor PM
13
and its gate is connected to node N
13
. Also, an NMOS transistor NM
15
in the schmitt trigger inverter
131
is coupled between the source of the PMOS transistor PM
13
and the source of the NMOS transistor NM
13
and its gate is connected to node N
13
which provides an input for the inverter INV
11
.
FIG. 3A
is a voltage wave form of the conventional schmitt trigger in FIG.
1
and
FIG. 3B
is a hysteresis loop illustrating voltage transfer characteristics for the conventional schmitt trigger in FIG.
1
.
Referring to
FIG. 3A
, the schmitt trigger inverter inverts the input signal VIN, by using a first voltage level VID as a reference voltage level for determining a high voltage level and a second voltage level VIU as a reference voltage level for determining a low voltage level. As a result, in case where the input signal VIN is larger than the first voltage level VID, the input signal VIN is considered as a high voltage level and, in case where the input signal VIN is smaller than the second voltage level VIU, the input signal VIN is considered as a low voltage level. Accordingly, when the input signal VIN is between the first voltage level VID and the second voltage level VIU, the schmitt trigger inverter may not positively work as an inverter. Accordingly, the schmitt trigger inverter doesn't have an effect on its output in case where there is a voltage variation between the first voltage level VID and the second voltage level VIU based on a glitch which is caused by a sudden increases in the supply of electric power.
Also, as shown in
FIG. 3B
, in case where the input signal VIN is in the vicinity of the first voltage level VID and the second voltage level VIU, the schmitt trigger inverter produces a dramatically inverted output signal irrespective of transition time of the input signal VIN. As set forth above, the schmitt trigger inverter has been used in improving the transition of the slow signal and in removing an input noise. Referring again to
FIG. 1
, when the activated power-on signal is applied to the capacitor C
11
, a potential at node N
11
rapidly increases in response to the power-on signal. Accordingly, the NMOS transistor NM
11
is turned on, node N
11
gradually goes into a pull-down mode, and then finally, the NMOS transistor NM
11
may be turned off. When the PMOS transistor PM
11
is turned on with the pull-down operation at node N
11
, the capacitor C
12
is charged and the output node N
12
of the input unit
110
is in a pull-up mode in such a way as to toggle the voltage level of the output node N
12
. After the output node N
12
in the input unit
110
is toggled once, node N
11
gradually goes into a pull-up mode and the PMOS transistor PM
11
is turned on and the output node N
12
goes into a pull-down mode. Namely, the output node N
12
of the input unit
110
, as an input signal of the schmitt trigger
130
, gradually goes from “low voltage level” to “high voltage level” or from “high voltage level” to “low voltage level”.
If the output node N
12
of the input unit
110
gradually goes from “low voltage level” to “high voltage level,” the schmitt trigger inverter
131
outputs an inverted low voltage level signal at the time when the input signal is higher than the first voltage level VID and, when the output node N
12
of the input unit
110
gradually goes from “high voltage level” to “low voltage level” and when the input signal is lower than the second voltage level VIU, the schmitt trigger inverter
131
outputs a toggled output signal from “high voltage level” to “low voltage level.
FIG. 2
is a block diagram illustrating another conventional power-on reset circuit. The power-on reset circuit in
FIG. 2
includes an input unit
210
to produce toggled signals in response to power-on signal, a schmitt trigger inverter
231
outputting a power-on reset signal in response to the toggled signals and a feed-back loop
270
feeding back an output signal of the schmitt trigger inverter
231
to the input unit
210
.
The input unit
210
has a PMOS transistor PM
21
, an NMOS transistor NM
21
and a capacitor C
21
. The PMOS transistor PM
21
receives an voltage level at node N
20
through its gate and transfers a power-on signal to a node
21
. The NMOS transistor NM
21
receives an voltage level at node N
20
through its gate and transfers a ground voltage level to the node
21
. Also, the capacitor C
21
, which is a MOS transistor having source and drain connected to a ground voltage level, is connected to the node
21
. A schmitt trigger inverter
231
is the same as that (the reference numeral
131
) in FIG.
1
. An output unit
250
connected to an output terminal (node N
23
) of the schmitt trigger inverter
231
latches and buffers an output signal of the schmitt trigger inverter
231
, having a plurality of inverters INV
21
to INV
25
. Further, the feed-back loop
270
includes an inverter INV
28
inverting a signal at node N
20
, an NAND gate ND
27
receiving output signals from the inverter INV
28
and the schmitt trigger inverter
231
, and inverters INV
26
and INV
27
for buffering an output signal of the NAND gate ND
27
.
When the power-on signal is activated, the PMOS transistor PM
21
is turned on by a low voltage level which is inputted into node N
20
and the MOS capacitor C
21
charges electric carriers. Accordingly, the output node N
23
gradually goes from a low voltage level to a high voltage level and the output terminal of the schmitt trigger inverter
131
is toggled from a high voltage level to a low voltage
Callahan Timothy P.
Hyundai Electronics Industries Co,. Ltd.
Nguyen Hai L.
LandOfFree
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