Method of generating tests for a combinational logic circuit

Details Method of generating tests for a combinational logic circuit Method of generating tests for a combinational logic circuit

1989-02-01

1991-02-26

MacDonald, Allen

Excavating

371 221, 371 27, G06F 1100

Patent

active

049966898

ABSTRACT:
In the present invention a method for generating tests for a combinational logic circuit of the PLA type is disclosed. The method is suited to generate tests to determine the input signals, the mid-term output signals of the AND gates, and the output signals, for stuck-at-0 and stuck-at-1 conditions.

REFERENCES:
patent: 3958110 (1976-05-01), Hong
patent: 4204633 (1980-05-01), Goel
patent: 4499579 (1985-02-01), Still
patent: 4672610 (1987-06-01), Salick
patent: 4716564 (1987-12-01), Hung
J. P. Roth, "Testing for Several Failures", IBM TDB, vol. 24, No. 7A, 12/1981, pp. 3259-3261.

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