Semiconductor device having circuit pattern and lands thereon

Details Semiconductor device having circuit pattern and lands thereon Semiconductor device having circuit pattern and lands thereon

2000-07-13

2002-10-15

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S779000, C257S784000, C257S786000

Reexamination Certificate

active

06465886

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip size package, i.e., a semiconductor device having substantially the same size as that of a semiconductor chip included therein.
2. Description of the Related Art
A chip size package (CSP) is a semiconductor device having substantially the same size as that of a semiconductor chip included therein and having an electrode terminal carrying surface including electrode terminals, electrically connected to external connection terminals, in the form of solder balls, etc.
FIG. 7
shows a cross-sectional view of a CSP including a semiconductor chip
10
and external connection terminals
12
, which are arranged entirely over an electrode carrying surface
11
of the semiconductor chip
10
that has a very small area. A protective film
14
protects the electrode carrying surface
11
.
FIG. 8
is a plan view showing an arrayed arrangement of external connection terminals
12
over the electrode carrying surface
11
of the semiconductor chip
10
. The arrangement of the electrode terminals
16
on the electrode terminal carrying surface
11
varies with the types of CSP
10
. The shown type of semiconductor chip includes the electrode terminals
16
arranged along the periphery of the electrode terminal carrying surface
11
and interconnection wiring lines
18
outwardly extending from the arrayed external connection terminals
12
to the electrode terminals
16
to provide electrical connection between the electrode terminals
16
and the external connection terminals
12
.
FIG. 9
is an enlarged partial cross-sectional view showing that the interconnection wiring lines
18
have a part forming a land
18
a
with a sufficient size for bonding to the external connection terminals
12
, i.e., the interconnection wiring lines
18
have one end bonded to the electrode terminals
16
and the other end forming the land
18
a
positioned for bonding to the external connection terminals
12
.
An insulating layer
20
covers the surface of the semiconductor chip
10
and has openings at positions corresponding to the electrode terminals
16
. After the insulating layer
20
having the openings is formed on the electrode terminal carrying surface
11
of the semiconductor chip
10
, a conductor layer is formed on the insulating layer
20
, by sputtering, etc., and is then patterned by etching to form the interconnection wiring lines
18
each having one end forming a land
18
a.
A chip size package has a problem that, as the number or density of the external connection terminals
12
is increased, the space between neighboring external connection terminals
12
becomes too small to allow the interconnection wiring lines
18
to run therethrough. There may be a case in which a plurality of interconnection wiring lines
18
must run through the space between neighboring external connection terminals
12
.
It is a continuing trend that CSPs will have a further increased number of in/out terminals or external connection terminals to provide multipin CSPs, and in an extreme case, it may not be possible to run interconnection wiring lines
18
through the space between neighboring external connection terminals
12
.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a CSP or a semiconductor device having substantially the same size as that of a semiconductor chip included therein, particularly a multipin CSP structure which enables interconnection wiring lines connecting electrode terminals with external connection terminals to be easily provided for semiconductor chips having increased number or density of external connection terminals as in/out terminals.
To achieve the object according to the present invention, there is provided a semiconductor device including a semiconductor chip having electrode terminals electrically connected to external connection terminals, the device comprising:
a semiconductor chip having an electrode terminal carrying surface including electrode terminals and interconnection wiring lines, each of the interconnection wiring lines having one end bonded to one of the electrode terminals and the other end forming a pad;
an insulating layer formed on the electrode terminal carrying surface to cover the electrode terminals, the interconnection wiring lines and the remaining area of the electrode terminal carrying surface;
conductor lands formed on the insulating layer, each of the conductor lands having a part forming a via extending through the insulating layer to the pad of one of the interconnection wiring lines; and
external connection terminals formed on the lands.
Typically, the pads are smaller in diameter than the lands. The via is preferably formed of a conductor layer coating a side wall and a bottom of a through hole penetrating the insulating layer, the bottom being defined by a surface of the interconnection wiring lines.
In a preferred embodiment, the lands occupy areas of the insulating layer that overlap areas of the electrode terminal carrying surface that are occupied by the interconnection wiring lines.


REFERENCES:
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5989991 (1999-11-01), Lien
patent: 0 469 216 (1992-02-01), None
patent: 59-181041 (1984-10-01), None
patent: 10-284634 (1998-10-01), None

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