Active solid-state devices (e.g. – transistors – solid-state diode – Tunneling pn junction device – Reverse bias tunneling structure
Reexamination Certificate
2001-06-19
2002-12-17
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Tunneling pn junction device
Reverse bias tunneling structure
C257S199000, C257S481000, C257S551000, C257S603000, C257S604000, C257S606000, C257S618000, C257S622000, C257S653000
Reexamination Certificate
active
06495863
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a technique effective for forming an input protection circuit of a MOS structure device.
2. Description of the Background Art
A MOS structure semiconductor element having a gate oxide film represented by a power MOSFET (metal oxide semiconductor field-effect transistor) or an IGBT (insulated gate bipolar transistor) requires an input protection circuit for protecting the semiconductor element against a surge current or static electricity, as well known in the art. When a surge current or static electricity flows into a gate electrode of the MOS structure semiconductor element, remarkable deterioration is readily caused on the electrostatic characteristic of a gate insulator film of the MOS structure semiconductor element. In general, therefore, a bidirectional Zener diode is provided between a gate electrode and a source electrode of a power MOSFET as the aforementioned input protection circuit, as shown in an equivalent circuit of FIG.
39
. Such a countermeasure is disclosed in the description of paragraph [0002] and FIG. 4 in Japanese Patent Application Laid-Open Gazette No. 7-321305 (1995), for example.
FIG. 40
is a top plan view showing the layout of a semiconductor device having a plurality of MOS structure semiconductor elements and an input protection circuit therefor, which is also employed in later description of an embodiment 1 of the present invention and modifications thereof.
FIG. 41
is a top plan view schematically showing an input protection Zener diode forming region hatched in
FIG. 40
among regions formed on the upper surface of a base layer of the aforementioned semiconductor device in an enlarged manner. The input protection Zener diode forming region is hereinafter referred to as a first region, and a region formed with a MOS transistor structure having a gate electrode and a main electrode is referred to as a second region. The definition of these regions also applies to later description of the embodiment 1, an embodiment 2 and modifications thereof. As shown in
FIG. 41
, a Zener diode is formed by alternately forming p-type semiconductor layers and n-type semiconductor layers in the form of rings.
FIG. 42
is a longitudinal sectional view of the Zener diode taken along the line I-II in FIG.
41
.
FIG. 43
is a longitudinal sectional view of an n-type diffusion region (n-type semiconductor layer) of the Zener diode taken along the line III-IV in FIG.
41
.
As shown in
FIGS. 41
to
43
, an n-type second semiconductor substrate
2
containing low-concentration n-type impurities is formed on an n-type first semiconductor substrate
1
containing high-concentration n-type impurities by epitaxy. The substrates
1
and
2
form an n-type base semiconductor layer. Further, an insulator film
3
of an oxide film or the like is formed on the base semiconductor layer (
1
,
2
). An input protection circuit is formed on a base layer defined by the base semiconductor layer (
1
,
2
) and the insulator film
3
by the following manufacturing method: A polysilicon layer
4
is formed on the base layer, for successively forming an n-type semiconductor layer
4
b
1
having a square cross-sectional or planar shape, a p-type semiconductor layer
4
a
1
having a ring cross-sectional shape, a ring-shaped n-type semiconductor layer
4
b
2
, a ring-shaped p-type semiconductor layer
4
a
2
and a ring-shaped n-type semiconductor layer
4
b
3
in the polysilicon layer
4
to enclose a gate pad formed after formation of the Zener diode. Thus, a bidirectional Zener diode having a plurality of p-n junction surfaces is formed as the input protection circuit.
Thereafter the Zener diode is overcoated with an interlayer isolation film
5
, and contact holes
6
a
and
6
b
are provided on portions located immediately above the innermost n-type semiconductor layer
4
b
1
and the outermost n-type semiconductor layer
4
b
3
of the ring-shaped Zener diode respectively for bringing the n-type semiconductor layers
4
b
1
and
4
b
3
into ohmic contact with a gate electrode layer
7
a
and a source electrode layer
7
b
through the contact holes
6
a
and
6
b
respectively. Thereafter another interlayer isolation film (not shown) is formed on the gate electrode layer
7
a
and the source electrode layer
7
b
and an opening is formed in part of this interlayer isolation film located on the gate electrode layer
7
a
, thereby partially exposing the gate electrode layer
7
a
. The exposed part of the gate electrode
7
a
defines the aforementioned gate pad.
A reverse withstand voltage of the aforementioned Zener diode is set to a desired value by adjusting the number of the p-type and n-type semiconductor layers forming the Zener diode or adjusting the impurity concentrations of the p-type and n-type semiconductor layers.
For example, Japanese Patent Application Laid-Open Gazettes Nos. 7-321305 (1995), 8-288525 (1996) and 9-97901 (1997) disclose a Zener diode having a structure corresponding to such a longitudinal sectional structure.
The input protection circuit having the aforementioned structure protects the gate insulator film of the MOS structure semiconductor element against a surge current or static electricity. However, the effect of the conventional input protection circuit for protecting the gate insulator film cannot still be said sufficient since the value of parasitic resistance of the diode in the conventional input protection circuit is unignorably large due to the specification of the apparatus. Consider that surge takes place, for example. Also when feeding a surge current from the gate electrode toward the source electrode through the aforementioned diode at this time, a voltage determined by the product of the parasitic resistance value of the diode and the surge current is applied across the diode, to cause remarkable deterioration in characteristics of the gate oxide film as the case may be. In other words, it follows that characteristic deterioration of the gate oxide film readily takes place as the parasitic resistance value of the diode is increased regardless of the surge current flowing to the diode, to remarkably damage the function of the diode serving as the input protection circuit.
Such a problem is caused also when static electricity is generated in the MOS structure semiconductor element.
It is well known that the parasitic resistance value of the diode is inversely proportionate to the peripheral length (corresponding to the length of the diode or each semiconductor region shown in
FIG. 41
in a peripheral direction PD) of the diode and the thickness of the polysilicon layer in each p-n junction surface and proportionate to the width (corresponding to the length in a direction perpendicular to the peripheral direction PD) of each semiconductor region in the diode.
Therefore, the peripheral length of the diode or the thickness of the polysilicon layer may be increased or the width of each semiconductor region may be reduced thereby reducing the parasitic resistance value of the diode and improving the function of the diode serving as the input protection circuit.
When simply increasing the peripheral length of the diode, however, a new problem arises to enlarge the chip size. When the area occupied by the diode itself, inclusive of the area occupied by the gate pad, is increased, the peripheral length of the diode is also increased in response thereto, while activation regions of the MOS transistors are narrowed to result in such a problem that the number of the MOS transistors cannot be increased to a necessary level. Occurrence of such a problem is serious particularly in a semiconductor device originally having a small chip size.
While increase of the thickness of the polysilicon films employed for the diode brings reduction of manufacturability, while such a structural restriction results from increase of the thickness of the polysilicon layers that
Brock II Paul E
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wilson Allan R.
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