Fishing – trapping – and vermin destroying
Patent
1993-11-23
1994-08-30
Thomas, Tom
Fishing, trapping, and vermin destroying
437 56, 437200, 437913, 148DIG117, 148DIG147, H01L 21265
Patent
active
053427980
ABSTRACT:
Selective salicidation of source/drain regions of a transistor is accomplished by performing an implant into a first plurality of transistor source/drain regions on an integrated circuit. As a result of the implant, doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit. The integrated circuit is heated to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The heating temperature is chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions. A metal layer is formed over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The metal layer is annealed at a temperature such that the metal reacts to form metal-silicide over the second plurality of transistor source/drain regions, but not over the first plurality of transistor source/drain regions. The unreacted metal is stripped off over the first plurality of transistor source/drain regions.
REFERENCES:
patent: 4627153 (1986-09-01), Masuoka
patent: 4866002 (1989-09-01), Shizukuishi et al.
patent: 4874713 (1989-10-01), Gioia
patent: 5106768 (1992-04-01), Kuo
patent: 5187122 (1993-02-01), Bonis
patent: 5194405 (1993-03-01), Sumi et al.
patent: 5262344 (1993-11-01), Mistry
Y. Wei, Y. Loh, C. Wang and C. Hu, MOSFET Drain Engineering for EDS Performance, EOS/ESD Symposium, 1992, pp. 143-148.
Silicon Processing for the VLSI Era--vol. 2, Process Integration, pp. 144-152, 154, 155, 1986.
C. Duvvury, R. N. Rountree, Y. Fong, and R. A. McPhee, ESD Phenomena and Protection Issues in CMOS Output Buffers, IEEE/IRPS, 1987, pp. 174-180.
D. Krakauer, K. Mistry, ESD Proection in a 3.3 Volt Sub-Micron Silicided CMOS Technology, EOS/ESD Symposium, 1992, pp. 250-257.
T. Yamaguchi, et al., High-Speed Latchup-Free 0.5.mu.m-Channel CMOS Using Self-Aligned TiSi.sub.2 and Deep-Trench Isolation Technologies, IEDM 83, 243., 1983, pp. 522-525.
Thomas Tom
Trinh Michael
VLSI Technology Inc.
Weller Douglas L.
LandOfFree
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