Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-10-31
2002-06-11
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185180, C365S185260, C365S185280
Reexamination Certificate
active
06404681
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for erasing data from a non-volatile semiconductor memory device. More particularly, the present invention relates to a method for erasing data from a non-volatile semiconductor memory device which employs a write method using channel hot electrons. 2. Description of the Related Art
An ETOX (registered trademark of Intel; EPROM Thin Oxide) type non-volatile semiconductor memory device is the most widely used conventional non-volatile semiconductor memory device (a flash memory). Japanese Patent Publication for Opposition No. 6-82841 (Conventional Example 1) discloses a non-volatile semiconductor memory device of this type. Referring to
FIG. 1
, the structure of a cell of an ETOX type non-volatile semiconductor memory device will be described. The non-volatile semiconductor memory device cell includes a source
14
a
and a drain
14
b
which are formed on a substrate
10
, with a channel layer
14
c
extending therebetween. A floating gate
16
is provided over the channel layer
14
a
via a tunnel oxide film
15
. Moreover, a control gate
18
is provided over the floating gate
16
via an interlayer insulating film
17
.
The principle of operation of an ETOX type non-volatile semiconductor memory device will now be described. Table 1 shows voltages to be respectively applied to the control gate
18
, the drain
14
b
, the source
14
a
and the substrate
10
in a write mode, an erase mode, and a read mode.
TABLE 1
Control
gate
Drain
Source
Substrate
Write
10 V
6 V/0 V
0 V
0 V
Erase
−9 V
Open
6 V
0 V
Read
5 V
1 V
0 V
0 V
In the write (programming) mode, a voltage of 10 V, for example, is applied to the control gate
18
of the memory cell to which data is to be written, a reference voltage of 0 V, for example, is applied to the source
14
a
thereof, and a voltage of 6 V, for example, is applied to the drain
14
b
. A large current of 500 &mgr;A/cell flows through the channel region
14
c
, thereby generating channel hot electrons (hereinafter, referred to as “CHEs”) in a portion of the drain
14
b
side of the memory cell where there is a high electric field. Basically, CHEs are high-energy electrons which are generated by a high electric field and which flow through the channel. When CHEs jump over the energy barrier of the tunnel oxide film so as to be injected into the floating gate
16
, the threshold voltage of the memory cell increases. The drain of each memory cell (non-selected memory cell) to which no data is to be written is set to a reference voltage (e.g., 0 V). The memory cell to which data has been written as described above has a threshold voltage equal to or greater than 5.5 V as shown in
FIG. 2
by the curve labelled “Programmed state (a)”. As shown in
FIG. 2
, each memory cell whose threshold voltage is equal to or less than 3.5 V is in an erased state, and each memory cell whose threshold voltage is equal to or greater than 5.5 V is in a written (programmed) state.
In the erase mode, a voltage of −9 V, for example, is applied to the control gate
18
and a voltage of 6 V, for example, is applied to the source
14
a
, whereby electrons are withdrawn from the floating gate
16
on the source
14
a
side of the memory cell, thereby reducing the threshold voltage. In such a case, the memory cell has a threshold voltage as shown in
FIG. 2
by the curve labelled “Erased state (b)”. Thus, the threshold voltage of the memory cell whose data has been erased is less than or equal to 3.5 V.
FIG. 3
illustrates how electrons are withdrawn from the source side. In the erase operation, a BTBT (band to band tunneling) current flows through the device, as shown in FIG.
3
. Simultaneously with this current flow, hot holes and hot electrons are generated. While the hot electrons flow into the substrate, the hot holes are drawn toward the tunnel oxide film and trapped therein. It is believed in the art that this trapping degrades the reliability of the device.
For a memory cell to/from which data has been written/erased, a read operation can be performed by applying a voltage of 5 V to the control gate
18
and a voltage of 1 V to the drain
14
b
, while controlling the potential of the source
14
a
to be 0 V. Under such voltage conditions, if data stored in the memory cell is in the erased state, the threshold voltage of the memory cell is less than or equal to 3.5 V. Therefore, a current flows through the memory cell, which is detected by a sense circuit (not shown) connected to the drain, whereby the data in the memory cell is determined to be “1” (i.e., in the erased state). If data stored in the memory cell is in the written state, the threshold voltage of the memory cell is equal to or greater than 5.5 V, and no current flows through the memory cell, whereby the data in the memory cell is determined by the sense circuit to be “0” (i.e., in the written state).
The write, erase and read operations are performed according to such a principle of operation. In an actual device, the erase operation is performed in a relatively larger unit of blocks, e.g., by 64-kB blocks. Within each block to be erased, the memory cells have varied threshold voltages because some of the memory cells have data in the programmed state and other memory cells have data in the erased state. Therefore, it is necessary to perform the erase operation by using a complicated algorithm as shown in
FIG. 4
(Japanese Laid-Open Publication No. 9-320282).
The erase method shown in
FIG. 4
will now be described. When the erase operation is initiated, all of the memory cells in one block are brought into a written state by an ordinary write operation (the write method using CHEs) (step S
1
).
Next, a program verify operation is performed by 8-bit blocks (step S
2
) for verifying that the threshold voltage of the memory cell to which data has been written in step S
1
is equal to or greater than 5.5 V. If the threshold voltage of the memory cell is not equal to or greater than 5.5 V, the process returns to step S
1
to continue the write operation. If the threshold voltage is equal to or greater than 5.5 V, the process proceeds to step S
3
.
In step S
3
, an erase pulse is applied to the memory cells by blocks. Data is erased from a memory cell by withdrawing electrons from the source side of the memory cell so as to reduce the threshold voltage thereof. Next, in step S
4
, an erase verify operation is performed for verifying that the threshold voltage of each of the memory cells in the block is less than or equal to 3.5 V. If the threshold voltage of the memory cell is not less than or equal to 3.5 V, the process returns to step S
3
to continue the erase operation. If the threshold voltage of the memory cell is less than or equal to 3.5 V, the erase operation is completed.
As can be seen, in the erase method of
FIG. 4
, all of the memory cells in a block to be erased are first brought to a written state so that the threshold voltage distribution after the erase operation is as narrow as possible and that there are no over-erased cells (i.e., a cell whose threshold voltage is less than or equal to 0 V). This write operation can be performed for eight memory cells at once by an ordinary program operation. If the write time for one memory cell is 2 &mgr;s, the amount of time required for this write operation (or the pre-erase write time) is obtained as follows:
2 &mgr;s×64 kB/8=131 ms
If the total erase time is 600 ms, the pre-erase write time accounts for about 20% of the total erase time. The pre-erase write time of 131 ms holds in the case where a 5 V power source is used, and increases to 262 ms in the case where a 3 V power source is used. This is because when a 3 V power source is used, the capability of the charge pump for increasing the supply voltage to obtain the pre-erase write voltage, e.g., the voltage applied to the control gate, is poor, so that the pre-erase write operation can be performed for only 4 bits at a time, thereby resulting in the increase in the pre
Ho Hoai V.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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