Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1996-07-08
2002-11-12
Moe, Aung S. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S303000
Reexamination Certificate
active
06480228
ABSTRACT:
BACKGROUND OF THE INVENTION
In general, the present invention relates to a solid-state image sensing device which employs solid-state image sensing elements which serve as area or linear sensors. In particular, the present invention relates to a solid-state image sensing device which clamps a signal output by a solid-state image sensing element thereof to a predetermined reference potential.
RELATED ART
In a solid-state image sensing device employing CCD solid-state image sensing elements such as CCD linear sensors as shown in
FIG. 1
, differential operations are carried out at a signal processing unit
15
at a later stage by clamping a black level or holding samples in order to compensate for an offset due to the optical transmission through a CCD shift register (serving as an electric-charge transferring unit)
13
for transferring signal electric charge read out from a sensor array
11
and to cancel dark-current components.
An actual circuit configuration of the signal processing unit
15
is shown in FIG.
2
. Here, by the black level, the level of picture element signals at shading units
11
a
and
11
b
which are also referred to as optical black (OPB) units at the sensor array
11
is meant. The shading units
11
a
and
11
b
are also referred to hereafter as a second OPB unit and a first OPB unit respectively.
In order to process digitally a signal output Vout, an A/D converter
16
is provided at a later stage of the signal processing unit
15
. The signal output Vout, a clamped output of a clamp circuit
22
, is converted into a digital signal by the A/D converter
16
. In this case, by setting the clamp level of the clamp circuit
22
at a reference potential Vref of the A/D converter
16
, a wide input D (dynamic) range of the A/D converter
16
can be utilized. In general, the reference potential Vref of the A/D converter
16
is set at the maximum level of the input D range.
When only the picture element signal output by the first OPB unit
11
b
is clamped to the reference potential Vref of the A/D converter
16
in the clamp processing of this black level, a dark current and offset due to the optical transmission through the CCD shift register
13
may be raised to a higher level. In this case, the signal level at the empty transmission unit
13
a
of the CCD shift register
13
becomes higher than the level of the picture element signals of the OPB units
11
a
and
11
b
by a difference caused by the dark current and the like. Accordingly, if its clamped output is supplied to the A/D converter
16
as it is, a signal voltage higher than the reference potential Vref, which is set at the maximum level of the D range, will be input to the A/D converter
16
. As a result, such a configuration gives rise to problems that the A/D converter
16
does not function correctly and data resulting from the A/D conversion is therefore damaged. On the top of that, if the worst comes to the worst, the A/D converter
16
itself is damaged.
In addition, the signal output by the empty transmission unit
13
a
of the CCD shift register
13
can also be clamped to the reference potential Vref of the A/D converter
16
. In this case, the D range of the A/D converter
16
that can be used for the signal becomes narrower by the dark-current portion. On the top of that, when the dark-current portion changes due to a change in temperature or the like, the level of the image sensing picture element signal is also shifted by a displacement determined by the dark-current portion. As a result, signal processing for subtracting the dark-current portion and the like is required, inevitably making the circuit configuration accordingly complicated.
In order to solve the problems described above, a solid-state image sensing device is disclosed in Japanese Patent Laid-open No. Hei 7-30820 with a configuration wherein a timing generator
17
generates clamp pulses &phgr;CLP
1
and &phgr;CLP
2
for clamping the signals of the empty transmission unit
13
a
of the CCD shift register
13
and the OPB unit
11
b
on the rear side of the sensor array
11
respectively each over a period of time corresponding to one picture element as shown in timing charts of FIG.
22
. The clamp pulse &phgr;CLP
1
is set with clamp timing for a signal portion of a signal output by the empty transmission unit
13
a
of the CCD shift register
13
corresponding to the first picture element while the clamp pulse &phgr;CLP
2
is set with clamp timing for a portion of a signal output by the OPB unit
11
b
on the rear side of the sensor array
11
corresponding to the second picture element or a subsequent one. On the other hand, the A/D conversion is carried out by the A/D converter
16
on a later stage with timing not to sample a portion of a signal output by the empty transmission unit
13
a
of the CCD shift register
13
corresponding to the first picture element.
It should be noted that notation &phgr;ROG shown in timing charts of
FIG. 22
denotes a read gate pulse which is applied to a shift gate
12
for reading out signal electric charge from the sensor array
11
. Notations &phgr;H
1
and &phgr;H
2
are transfer clocks of the CCD shift register
13
whereas notation &phgr;RS is a reset pulse for resetting an detecting unit
14
. Notation &phgr;SH is a sample/hold pulse for a sample/hold circuit
21
of a signal processing unit
15
. Notation Va is a sample/hold signal output by the sample/hold circuit
21
whereas notation &phgr;CLP (strictly speaking, notations &phgr;CLP
1
and &phgr;CLP
2
) are clamp pulses of a clamp circuit
22
. Notation Vout denotes a signal output. In the conventional solid-state image sensing device with the configuration described above, a portion of a signal output by the empty transmission unit
13
a
of the CCD shift register
13
corresponding to the first picture element is clamped by the clamp pulse &phgr;CLP
1
. However, a technique for preventing a signal voltage higher than the reference potential Vref of the A/D converter
16
from being supplied to the A/D converter
16
over an entire period of the empty transmission is not taken into consideration.
When signal electric charge is read out from the sensor array
11
to the CCD shift register
13
by application of the read gate pulse &phgr;ROG, by halting transfer clock signals &phgr;H
1
and &phgr;H
2
, the transfer operation carried out by the CCD shift register
13
is suspended temporarily. In this transfer suspension period, no signal electric charge is injected into an FD unit of the electric-charge detecting unit
14
. On the top of that, by applying a reset pulse &phgr;RS, a reset state is established, putting the detection output of the electric-charge detecting unit
14
at the highest potential. As a result, by merely clamping a portion of a signal output by the empty transmission unit
13
a
corresponding to the first picture element using the clamp pulse &phgr;CLP
1
, a high voltage (a) in the transfer suspension period generated thereafter is supplied as it is to the A/D converter
16
as a signal output Vout.
In addition, in the case of the conventional technology described above, the operation to clamp a portion of a signal output by the empty transmission unit
13
a
corresponding to the first picture element using the clamp pulse &phgr;CLP
1
prevents a signal voltage higher than the reference potential Vref of the A/D converter
16
from being supplied to the A/D converter
16
only during a minimum unit time of the empty transmission period. On the other hand, the A/D converter
16
does not sample a portion of a signal output by the empty transmission unit
13
a
corresponding to the first picture element. As a result, a signal voltage higher than the reference potential Vref of the A/D converter
16
is not supplied to the A/D converter
16
. In order to implement this scheme, however, the sampling time of the A/D converter
16
must be set so that a portion of a signal output by the empty transmission unit
13
a
corresponding to the first picture element is not sampled, giving rise to a diffic
Maki Yasuhito
Yoshihara Satoshi
Kananen Ronald P.
Moe Aung S.
Rader & Fishman & Grauer, PLLC
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