High-speed sense amplifier capable of cascade connection

Details High-speed sense amplifier capable of cascade connection High-speed sense amplifier capable of cascade connection

2000-02-17

2002-02-26

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C527S315000

Reexamination Certificate

active

06351155

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to sense amplifiers, and more particularly, to a clocked CMOS differential sense amplifier having high speed and high output.
BACKGROUND OF THE INVENTION
Clocked sense amplifiers present a wide range of different circuit implementations, but in most cases, a cross-coupled transistor structure serves as a basis for the sense amplifier. The differences between various implementations relates to methods of imbalancing the cross-coupled nodes before or during the clock pulse edge.
FIG. 1
shows a typical differential clocked sense amplifier. Transistors MP
1
, MP
2
, MN
1
, MN
2
form a cross-coupled complementary structure. Transistor MN
5
which is controlled by a strobe pulse, serves as a current source. Transistors MP
3
, MP
4
are used for precharging cross-coupled output nodes Q and NQ to the supply voltage when the current source MN
5
is off. Transistors MN
3
, MN
4
provide different discharging currents in accordance with the imbalance in voltages at input nodes I and NI, when the current source MN
5
turns on. The different discharging currents leads to different voltages at the output nodes Q and NQ. Because of the positive feedback, the output node with the lower potential will be pulled even lower, and the other output node will go back toward the supply voltage.
The speed and loading characteristics of any cross-coupled sense amplifier depend on the conductivity of the discharging chain and the capacitances of the cross-coupled nodes. The higher the conductivity and the lower the capacitance, the higher the speed and the output of an amplifier. Typical sense amplifiers have a discharging chain formed with three n-channel transistors, for example, MN
1
, MN
3
, MN
5
in
FIG. 1
, which are connected in series. This leads to some limitation of conductivity. The capacitances of the cross-coupled nodes are composed of the drain capacitances of one p-channel and n-channel cross-coupled transistor pair, gate capacitances of the opposite pair and the drain capacitance of recovery transistor MP
3
. The P-channel transistors MP
1
, MP
2
must be relatively large, because up to the rising edge of the clock pulse they both are off, and only when the lower cross-coupled node reaches Vdd—Vtp (where Vtp is the threshold voltage of p-channel transistor) one of them starts to conduct to provide the recovery of the opposite node to the supply voltage. The P-channel transistors MP
3
, MP
4
must be large also to provide for the recovery of the discharged node to Vdd in a reasonable time. So, the capacitances of the cross-coupled nodes are significant, and concerning their discharging ability, include some parasitic components.
SUMMARY OF THE INVENTION
The present invention provides a clocked CMOS sense amplifier for high speed latching of low voltage complementary signals. The basic sense amplifier includes a controlled cross-coupled transistor structure, a control circuit, a current source, a recovery transistor and protective transistors. A CORE circuit is provided which may be used to form different logic structures. Two large n-channel transistors in a discharging chain are used in combination with the small capacitances of the cross-coupled nodes to provide maximum speed and high output.
In one embodiment of the present invention, a sense amplifier core is provided that includes a first PMOS pair that outputs complementary low voltage input signals, a cross-coupled NMOS pair with common source and drain for latching the complementary low voltage input signals and wherein a feedback signal is coupled between the NMOS pair and the first PMOS pair, a control circuit coupled to the first PMOS pair, and a second PMOS pair coupled to the first PMOS pair for preventing the complementary low voltage input signals from drifting.
Another aspect of the present invention relates to an accessory circuit for improving the recovering characteristics of the sense amplifier for use at high clock frequencies.
Another aspect of the present invention relates to an accessory circuit for output buffering of the sense amplifier for large load applications.
Another aspect of the present invention relates to an accessory circuit for input level conversion of the sense amplifier for use with half-supply voltage pre-charge of the input lines.
Another aspect of the present invention relates to a cascade connection of the sense amplifier cores in combination with n-channel current sources for performing logic functions.
Another aspect of the present invention relates to a complementary circuit of the sense amplifier wherein n-channel transistors are substituted with p-channel transistors (or vice versa) and the input lines are pre-charged to ground potential.


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