Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-04-09
2002-06-11
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S536000
Reexamination Certificate
active
06404274
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a chip internal voltage generating circuit for generating internal voltages for a semiconductor integrated circuit and a semiconductor memory using the internal voltage generating circuit and, more particularly, to a voltage setting circuit for setting a plurality of variable potentials and a semiconductor memory using the voltage setting circuit, which are used, e.g., for a data write/erase multi-level voltage generating circuit for a nonvolatile semiconductor memory.
A single power supply has recently been employed in a semiconductor integrated circuit incorporating an electrically programmable and erasable nonvolatile memory, e.g., an EEPROM or flash memory. When a single power supply is used, an internal voltage generating circuit provided in a chip generates a high voltage required to write or erase data.
Such an internal voltage generating circuit includes a charge pump circuit which generates a high voltage from the an externally applied power supply voltage and a voltage limiter circuit for adjusting the output voltage from the charge pump circuit to a desired voltage value (internal voltage).
In consideration of variations in characteristics of wafers or chips, it is essential to add a trimming circuit to the voltage limiter circuit. In some case, a generated internal voltage may be intentionally stepped up to be used for write or erase operation.
Under the circumstances, it is desired that the voltage range and the step-width of the above voltage limiter circuit can freely be designed in accordance with the application purpose. It is therefore preferable that the above voltage limiter circuit allows arbitrary setting of a set voltage range and the width of voltage steps.
FIG. 7
shows an equivalent circuit of a conventional internal voltage generating circuit for generating internal voltages, such as write and erase voltages in an EEPROM or flash memory.
Referring to
FIG. 7
, a voltage limiter circuit is connected to an output node
10
of a charge pump circuit (CP)
70
generating a given internal voltage. In this voltage limiter circuit, a load resistor RL having a constant resistance is connected in series to an equivalent resistor R
1
′ of a trimming circuit
20
for setting the voltage value of output node
10
. Resistors RL and R
1
′ are arranged between the output node
10
of the charge pump circuit
70
and a ground potential Vss.
A comparison output VXXFLG is generated by voltage comparing circuit
13
comparing the potential at a connection node N
1
between the resistor elements RL and R
1
′ with a reference voltage Vref. This comparison output VXXFLG is fed back to the charge pump circuit
70
through a CP control circuit
17
to control the boosting operation of the charge pump circuit
70
so as to make the potential at the connection node N
1
equal to the reference voltage Vref. As a result, an output voltage VXX from the output node
10
is controlled to be constant.
FIG. 8
shows an equivalent circuit of a resistance-type potential dividing D/A conversion circuit, which is a conventional arrangement of trimming circuit
20
as shown in FIG.
7
.
This trimming circuit comprises division resistors R
1
-
1
, R
1
-
2
, . . . , R
1
-m connected in series, MOS transistors T
1
, T
2
, . . . , Tm serving as switches, each having one terminal connected to corresponding one of the resistors at one terminal closer to the ground potential and having the other terminal commonly connected to the ground potential Vss, and a decoder circuit
21
for decoding control data B
1
, B
2
, . . . , Bn (n-bit data) to supply control signals D
1
, D
2
, . . . , Dm for selectively turning on one of the MOS transistors.
The output voltage VXX at the output node
10
of the charge pump circuit
70
in
FIG. 7
can be expressed by:
VXX=V
ref+(
V
ref·
RL
)/
R
1
′ (1)
As is obvious from equation (1) above, the output voltage VXX can be adjusted by adjusting the resistance value of the equivalent resistor element R
1
′ in the trimming circuit
20
thereby to change the potential at a connection node N
10
.
In the circuit arrangements shown in
FIGS. 7 and 8
, both the absolute value of the output voltage VXX and a voltage step width are determined by the load-resistor element RL and the resistor element R
1
′ subjected to trimming. In other words, when the resistance values of the resistor element R
1
′ and the load resistor element RL change, both the value of the output voltage VXX and voltage step width may vary.
If, therefore, the range of the output voltage VXX required is changed, the value of the equivalent resistor element R
1
′ of the trimming circuit
20
must be determined again to keep the voltage step width unchanged (As for the circuit of
FIG. 8
, it will be necessary to set again the resistance value of each of the resistors R
1
-
1
to R
1
-m.) The same problem occurs in the case that only the voltage step width is changed. Further, The same applies to a processed chip. For example, when the resistance values of the resistor elements R
1
′ and RL are changed by adding or removing interconnections (resistance components) by FIB process, there occurs a problem such that the voltage step as well as the range of the output voltage width is change.
More specifically, in the conventional internal voltage generating circuit shown in
FIGS. 7 and 8
, the degree of freedom in determining a set voltage range, the minimum set voltage, and the number of voltage steps is low. When the minimum set voltage changes, the voltage step width also changes. In addition, since decoder circuits, each identical to the decoder circuit
21
for generating control signals, are required in accordance with the number of set voltages, the arrangement is complicated, and the number of elements used increases.
For example, to make the voltage limiter circuit generate set voltages corresponding to 16 steps, the trimming circuit
20
requires 16 pairs of division resistors R
1
-I (I=
1
,
2
, . . . , m). and MOS transistors Ti, 16 interconnections for control signals Di to be input to the gates of the MOS transistors Ti, and 16 4-input decoder circuits each serving as the decoder circuit
21
for decoding 4-bit digital data.
In general, if a trimming step count is 2
N
, 2
N
division resistors and 2
N
N-input decoders corresponding to N-bit digital inputs are required.
As the value of N increases, the number of elements such as the decoder circuits
21
and division resistors abruptly increases. As a consequence, the pattern area of the trimming circuit
20
increases, resulting in difficulty in circuit design. In addition, the degree of freedom in pattern change is low with respect to manufacturing variations in resistance value. This makes it more difficult to make a design change for the adjustment of resistance values.
A conventional multi-level high power generating circuit for an EEPROM to which the internal voltage generating circuit is applied will be described next.
Among EEPROMs, a NAND cell type flash memory using an array of cell units (NAND cells) each consisting of a plurality of series-connected memory cells is known as a memory that allows high integration and batch erase operation.
Each memory cell of a NAND cell type flash memory has a MOSFET structure in which a floating gate (charge storage layer) and a control gate are stacked, through an insulating film, on a semiconductor substrate on which source and drain regions are formed. A NAND cell is formed by connecting a plurality of memory cells in series with each other with adjacent memory cells sharing sources and drains. Such NAND cells are arranged in the form of a matrix to form one memory cell array.
In this case, the respective bit lines extend in the column direction, and the drain on one end side of each of NAND cells arranged side by side in the column direction of the memory cell array is commonly connected to the bit lines through a corresponding selection gate tran
Hosono Koji
Itoh Yasuo
Takeuchi Ken
Hogan & Hartson L.L.P.
Le Dinh T.
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