Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-16
2002-12-31
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185020, C257S048000, C257S428000
Reexamination Certificate
active
06501683
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and more particularly relates to a non-volatile semiconductor memory device including gate electrodes in two layers, i.e., control and floating gates, and functioning as a flash memory.
Memories so constructed as to erase specified data electrically at a time, like a flash memory, have been in higher and higher demand these days.
As is well known in the art, various factors make it difficult for a flash memory to ensure high reliability. A so-called “charge buildup damage” is one of those factors that decrease the reliability of a flash memory. The charge build-up damage is done on the tunnel insulating film of a flash memory during a metallization process to fabricate the memory. More specifically, when metal interconnects are formed by dry etching and patterning processes, positive or negative electric charges are likely accumulated in the interconnects. And if the quantity of those charges accumulated is huge, the control gate of the memory will have a potential with an outstandingly large absolute value, thus placing an excessively intense electric field on the tunnel insulating film. Should damage of that type be done on the tunnel insulating film, the reliability of a memory cell of the flash memory would decrease considerably.
For that reason, methods for reducing the charge buildup damage during a metallization process have been researched and developed vigorously in the pertinent art.
Hereinafter, one such method for reducing the charge buildup damage in a metallization process will be described.
FIG. 13
illustrates a memory cell for a flash memory (which will be herein called a “flash memory cell” simply) and a known charge buildup damage reducer. As shown in
FIG. 13
, a flash memory cell
101
has its control gate connected to a word line decoder
102
and to the cathode of a charge buildup damage reducer
103
. The charge buildup damage reducer
103
is implemented as a backward diode with a grounded anode.
FIG. 14
illustrates a cross-sectional structure for the damage reducer
103
. As shown in
FIG. 14
, a p-well
111
is defined in the upper part of a p-type semiconductor substrate
110
. Over the p-well
111
, n- and p-type doped regions
113
and
114
are defined and electrically isolated from each other by an isolation film
112
. The n-type doped region
113
is connected to the control gate of the flash memory cell
101
, while the p-well
111
and p-type substrate
110
are grounded by way of the p-type doped region
114
.
FIG. 15
illustrates a current-voltage (I-V) characteristic of the damage reducer
103
(i.e., backward diode). In FIG.
15
, the abscissa represents the voltage V
CG
applied to the control gate, while the ordinate represents the current I
diode
flowing from the n-type doped region
113
into the p-well
111
in the backward diode
103
. As shown in
FIG. 15
, if the voltage V
CG
applied to the control gate is V11 (e.g., about −0.6 V) or less, a forward bias is applied to the backward diode
103
. As a result, a current starts to flow through the backward diode
103
. On the other hand, if the voltage V
CG
applied to the control gate is V12 (e.g., about 15 V) or more, breakdown occurs at the backward diode
103
and a current also starts to flow through the diode
103
. That is to say, while the voltage V
CG
is between V11 (about −0.6 V) and V12 (about 15 V), no current flows through the backward diode
103
.
Next, it will be described how the known charge buildup damage reducer operates.
In a gate grounded erase method, in which electrons are removed from the floating gate by applying 0 V and 12 V to the control gate and source electrode, respectively, during erasing, the voltage applied to the control gate is always between 0 V and 12 V irrespective of the mode of operation the flash memory cell. No current flows through the backward diode within this voltage range, and the operation of the flash memory cell is not interfered with.
On the other hand, during the metallization process, positive or negative electric charges build up in the control gate of a flash memory cell. However, the known charge build-up damage reducer
103
, or the backward diode
103
, is connected to the control gate of the flash memory cell
101
. Accordingly, if the voltage applied to the control gate is V11 or less or V12 or more, the charges built up flow out of the control gate. In this manner, the damage done on the tunnel insulating film can be reduced and the considerable decrease in reliability of the flash memory is avoidable.
The known method of reducing the charge buildup damage in a metallization process, however, has the following two drawbacks.
Firstly, a negative voltage with a large absolute value cannot be applied to the control gate. As a flash memory cell has been downsized recently, it becomes more and more necessary to reduce the positive high voltage (e.g., about 12 V) applied to the source electrode during an erase operation. Various techniques of reducing the source voltage have been proposed. One of those methods is a gate negative voltage erase method as represented in the following Table 1:
TABLE 1
Write
Erase
Read
Non-
Non-
Non-
Selected
selected
Selected
selected
Selected
selected
Control gate
12 V
0 V
−8 V
0 V
5 V
0 V
Drain
5 V
Open
Open
Open
1 V
Open
Source
0 V
0 V
5 V
0 V
0 V
0 V
p-well
0 V
0 V
0 V
0 V
0 V
0 V
During a write operation, 12 V, 5 V, 0 V (i.e., ground potential) and 0 V are applied to the control gate, drain, source and p-well
111
of a selected flash memory cell, respectively. In this combination of applied voltages, channel hot electrons are created near the drain and are injected into the floating gate. After the write operation is over, the flash memory cell has a threshold voltage of about 6 V. As for non-selected flash memory cells on the other hand, 0 V is applied to the control gate thereof and the drain thereof is opened, thereby preventing those cells from being written erroneously.
During an erase operation, −8 V, 5 V and 0 V are applied to the control gate, source and p-well
111
of the selected flash memory cell and the drain thereof is opened. In this combination of applied voltages, a Fowler-Nordheim (FN) tunneling current flows from the floating gate into the source and the electrons are removed from the floating gate. After the erase operation is over, the flash memory cell has a threshold voltage of about 2 V. As for the non-selected flash memory cells on the other hand, 0 V is applied to the control gate and source thereof, thereby preventing those cells from being erased erroneously.
During a read operation, 5 V, 1 V, 0 V and 0 V are applied to the control gate, drain, source and p-well
111
of the selected flash memory cell, respectively. In this combination of applied voltages, where the memory cell selected has been erased, a current flows from the drain toward the source thereof. On the other hand, if the selected cell has been written, no current flows through the cell. Accordingly, by sensing a difference in the amount of current flowing from the drain to the source thereof, it is possible to determine whether the memory cell has been erased or written. As for non-selected flash memory cells on the other hand, the ground potential is applied to the control gate thereof and the drain thereof is opened, thereby preventing those cells from being read erroneously.
However, the known charge buildup damage reducer for metallization process is not applicable to a flash memory cell to which this gate negative voltage erase method is supposed to be applied. This is because the negative voltage of −8 V applied to the control gate thereof during the erase operation belongs to the voltage range in which the backward diode is forward biased, and cannot be applied to the control gate even when the damage reducer is used.
Secondly, the decrease in reliability of a flash memory cell is not completely avoidable because a positive high voltage of about 1
Matsushita Electric Co., Ltd.
Nguyen Viet Q.
Nixon & Peabody LLP
Studebaker Donald R.
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