Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-01-07
2002-11-26
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S758000, C257S761000, C438S622000, C438S625000, C438S638000, C438S678000
Reexamination Certificate
active
06486560
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of copper interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing electromigration in copper interconnect lines by doping their surfaces with barrier material using wet chemical methods.
BACKGROUND OF THE INVENTION
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-&mgr;m to 0.25-&mgr;m) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractory metals. Despite aluminum's (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. The copper (Cu) interconnect material may be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, electroless plating, and electrolytic plating.
However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon.
1
These problems have instigated further research into the formulation of barrier materials for preventing electromigration in both Al and Cu interconnect lines. In response to electromigration concerns relating to the fabrication of semiconductor devices particularly having aluminum-copper alloy interconnect lines, the industry has been investigating the use of various barrier materials such as titanium-tungsten (Ti—W) and titanium nitride (TiN) layers as well as refractory metals such as titanum (Ti), tungsten (W), tantalum (Ta), and molybdenum (Mo) and their silicides.
2
Although the foregoing materials are adequate for Al interconnects and Al-Cu alloy interconnects, they have not been entirely effective with respect to all-Cu interconnects. Further, though CVD has been conventionally used for depositing secondary metal(s) on a primary metal interconnect surface, CVD is not a cost-effective method of doping Cu interconnect surfaces with calcium (Ca) ions. Therefore, a need exists for a method of reducing electromigration in Cu interconnect lines by forming an interim protective layer from a chemical solution and a semiconductor device thereby formed.
1
Peter Van Zant, Microchip Fabrication: A Practical Guide to Semniconductor Processing,
3
rd Ed., p. 397 (1997).
2
Id., at 392.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution and a semiconductor device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to void formation rate. More specifically, the present invention provides a method of fabricating a semiconductor device having reduced electromigration in its Cu interconnect lines and a device thereby formed, the method comprising: A) providing a semiconductor substrate, the substrate having at least one via formed therein, each at least one via having a volume being optionally lined with a barrier layer; B) depositing a copper (Cu) seed layer in the at least one via for facilitating subsequent formation of at least one Cu interconnect line, the Cu seed layer lining the at least one via, the Cu seed layer comprising at least one intermediate Cu layer selected from a group of intermediate copper layers consisting essentially of: (1) a blanket Cu seed layer, and (2) a partial thickness Cu plated layer; C) treating the Cu seed layer in a chemical solution, thereby selectively forming a copper-calcium-X (Cu—Ca—X) conformal layer on the Cu seed layer, wherein X denotes at least one contaminant, and D) processing the Cu—Ca—X conformal layer by a technique selected from a group of techniques consisting essentially of: (1) proceeding to step E, (2) sputtering under an argon (Ar) atmosphere, and (3) treating in a plasma ambient, thereby effecting a thin Cu—Ca conformal layer on the Cu seed layer; E) annealing the thin Cu—Ca conformal layer onto the Cu seed layer, thereby removing the at least one contaminant, whereby the thin Cu—Ca conformal layer is alloyed, and thereby forming a contaminant-reduced Cu—Ca alloy surface on the Cu seed layer; F) electroplating the Cu—Ca alloy surface with Cu for filling the volume of the at least one via, thereby forming the at least one Cu interconnect line, and thereby forming at least one contaminant-reduced Cu—Ca/Cu interconnect structure, comprising the a contaminant-reduced Cu—Ca alloy surface on the Cu seed layer, in the via; G) annealing the at least one contaminant-reduced Cu—Ca/Cu interconnect structure, thereby forming at least one virtually void-less and contaminant-reduced Cu—Ca/Cu interconnect structure; H) chemical mechanical polishing the at least one virtually void-less and contaminant-reduced Cu—Ca/Cu interconnect structure and the optional barrier layer for forming a planarized surface; and I) completing formation of the semiconductor device. The annealing step primarily removes O and secondarily removes C and S, especially when performed in an environment such as a vacuum, an inert gas, and a reducing ambient such as an ammonia (NH
3
) plasma. Further, the present invention improves Cu interconnect reliability by enhancing electromigration resistance through impurity-level control, thereby balancing electromigration performance against low resistivity requirements.
REFERENCES:
patent: 6181012 (2001-01-01), Edelstein et al.
patent: 6417566 (2002-07-01), Wang et al.
patent: 6420258 (2002-07-01), Chen et al.
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Nguyen Tuan H.
Pham Thanhha
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