Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-10-30
2002-11-19
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S057000
Reexamination Certificate
active
06483353
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 2000-64218, filed Oct. 31, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to semiconductor devices that improve stability and amplification in semiconductor memory devices.
BACKGROUND OF THE INVENTION
Voltage sense amplifiers and/or current sense amplifiers are typically used to output data in semiconductor memory devices. Current sense amplifiers may be used more often because they may provide faster sensing speeds. A current sense amplifier typically receives current on a pair of input lines, amplifies the current as a voltage signal and outputs the amplified signal. The current sense amplifier uses a positive feedback circuit to provide an accurate current. These conventional current sense amplifiers may cause instability in the semiconductor device, such as oscillation of an output voltage.
Referring to
FIG. 1
, a detailed circuit diagram of conventional current sense amplifier circuits having a positive feedback circuit will be described. The current sense amplifier circuit consists of PMOS transistors MP
11
and MP
12
for sensing a current, NMOS transistors MN
11
and MN
12
for acting as a load resistance, and a switching transistor MN
13
. Currents I
1
and I
2
received over a pair of differential input/output lines IO and IOB (not shown) are input to input terminals IN and INB. PMOS transistors MP
11
and MP
12
are connected in a latch structure, i.e. the gates and drains of PMOS transistors MP
11
and MP
12
are cross coupled, and the drains of the PMOS transistors MP
11
and MP
12
are connected to an output terminal OUT and a complementary output terminal OUTB, respectively. The NMOS transistors MN
11
and MN
12
may be formed of diode-type transistors and may have the same resistance values. The switching transistor MN
13
is switched by an enable signal and allows the predetermined currents I
1
and I
2
supplied from the pair of differential input/output lines IO and IOB (not shown) to be directed to a ground voltage VSS.
It will be understood that in conventional current sense amplifiers, for example, the current sense amplifier of
FIG. 1
, it may be difficult to maintain and/or improve stability and amplification of the semiconductor device while effectively sensing the current of the semiconductor device. For example, in the case of the PMOS transistors MP
11
and MP
12
, a current difference &Dgr;I may be obtained using the following equations:
I
1
=−
g
mp
*v
outb
(1)
I
2
=−
g
mp
*v
out
(2)
&Dgr;
I=I
1
−
2
=
g
mp
(
v
out
−v
outb
) (3)
where I
1
and I
2
represent predetermined currents supplied from the pair of differential input/output lines IO and IOB, respectively, g
mp
represents the transconductance of PMOS transistors MP
11
and MP
12
, v
out
represents the output voltage of output terminal OUT, v
outb
represents the output voltage of complementary output terminal OUTB, and &Dgr;I represents the difference between first and second currents I
1
and I
2
, respectively.
Furthermore, in the case of NMOS transistors MN
11
and MN
12
, a current difference &Dgr;I may be obtained using the following equations:
I
1
=
g
mn
*v
out
(4)
I
2
=
g
mn
*v
outb
(5)
&Dgr;
I=I
1
−I
2
=g
mn
(
v
out
v
outb
) (6)
where I
1
and I
2
represent predetermined currents supplied from the pair of differential input/output lines IO and IOB, respectively, g
mn
represents the transconductance of NMOS transistors MN
11
and MN
12
, v
out
represents the output voltage of output terminal OUT, v
outb
represents the output voltage of complementary output terminal OUTB, and &Dgr;I represents the difference between first and second currents I
1
and I
2
.
Typically, the voltages and currents of NMOS transistors MN
11
and MN
12
and PMOS transistors MP
11
and MP
12
are the same, thus, g
mp
is typically equal to g
mn
. However, when g
mp
is larger than g
mn
, PMOS transistors MP
11
and MP
12
may amplify a larger current difference than the original current difference &Dgr;I, thus, reversing the voltages of the input terminals IN and INB. This may cause the voltages and currents of PMOS transistors MP
11
and MP
12
to be unstable. Thus, with respect to maintaining stability of the semiconductor device, g
mn
is preferably larger than g
mp
. On the other hand, when g
mn
is larger than g
mp
the current sense amplifier circuit may be less efficient and this may cause the sensing speed of the semiconductor device to deteriorate. Thus, a trade-off exists between stability of the semiconductor device and sensing speed of the semiconductor device and the transconductances g
mn
and g
mp
should be chosen accordingly. The modulation effects of a PMOS channel length is typically larger than the modulation effects of an NMOS channel length, thus, the larger a power supply voltage, the larger the transconductance g
mp
of the PMOS transistors MP
11
and MP
12
.
Now referring to
FIG. 2
, a diagram illustrating the current and/or voltage characteristics of transistors in conventional current sense amplifier circuits, for example, as shown in
FIG. 1
, will be described. Voltages V
gsn
and V
gsp
between the gates and the sources of the NMOS transistors and the PMOS transistors are illustrated on the horizontal axis, and the drain currents I
dn
and I
dp
of each of the NMOS and PMOS transistors are illustrated on the vertical axis. As illustrated, when the voltages V
gsn
and V
gsp
are larger than a predetermined voltage V
c
, the slope of a curve of current and/or voltage characteristics of the PMOS transistors MP
11
and MP
12
is larger than the slope of a curve of current and/or voltage characteristics of the NMOS transistors MN
11
and MN
12
. In this situation the transconductance g
mp
of the PMOS transistors is larger than the transconductance g
mn
of the NMOS transistors, and thus, the stability of the current sense amplifier circuit may deteriorate. Furthermore, as the power supply voltage increases, the stability of the current sense amplifier circuit continues to deteriorate, which may result in the inability to increase the amplification of an operation voltage. Consequently, the operation speed of a conventional current sense amplifier circuit may be slow and may be sensitive to noise.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.
In other embodiments of the present invention the first and second load devices may include first and second load transistors, respectively, that are connected as diodes. The latch may include first and second MOS transistors having crosscoupled drain and gates and may be responsive to a bias signal. The bias signal may be generated by a bias circuit that generates the bias signal on an output signal line in response to a control signal.
In further embodiments of the present invention, the bias circuit may include a first PMOS transistor having a source connected to a power supply voltage and a gate and a drain connected together. The circuit may further include a first NMOS transistor responsive to the control signal having a drain connected to the gate and drain of the first PMOS transistor and a source connected to the output signal line and second and th
Kim Chul-soo
Kim Joung-yeal
Myers Bigel & Sibley & Sajovec
Nu Ton My-Trang
LandOfFree
Current sense amplifier circuits containing latches for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Current sense amplifier circuits containing latches for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current sense amplifier circuits containing latches for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2976203