Semiconductor device with increased connection strength...

Details Semiconductor device with increased connection strength... Semiconductor device with increased connection strength...

2000-03-09

2002-11-26

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S737000, C257S700000

Reexamination Certificate

active

06486553

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to enhancement of a fabrication yield of a semiconductor device.
DESCRIPTION OF THE RELATED ART
In response to requirement for an electronic device to accomplish higher performance, to be smaller in size and lighter in weight, and to be able to operate at a higher rate, many new semiconductor devices have been developed. For instance, an electronic device is formed smaller in size and lighter in weight by more highly integrating a semiconductor chip to thereby fabricate a semiconductor device in smaller size and weight.
FIGS. 1A
to
1
C illustrate a conventional semiconductor device.
FIG. 1A
is a cross-sectional view of a conventional semiconductor device,
FIG. 1B
is an enlarged view of a connection between a wiring layer and a solder ball, and
FIG. 1C
is a cross-sectional view illustrating that the semiconductor device illustrated in
FIG. 1A
is electrically connected to a printed wiring board.
With reference to
FIG. 1A
, the conventional semiconductor device is comprised of a semiconductor chip
1
, a film substrate
3
, a polyimide adhesive layer
31
adhering the film substrate
3
to the semiconductor chip
1
, a resist
32
covering the wiring layer
2
therewith and formed with a land
7
which is a recess formed at a surface thereof, a wiring layer
2
formed on the film substrate
3
, a solder ball
101
mounted on the wiring layer
2
in the land
7
, a gold (Au) layer
8
covering the wiring layer
2
therewith within the land
7
, a metal
5
filled in a through-hole
4
formed through both the film substrate
3
and the polyimide adhesive layer
31
, and a gold (Au) layer
6
covering therewith the metal
5
at a top surface thereof
The wiring layer
2
is in electrical connection with the semiconductor chip
1
, and contains copper (Cu) therein. The solder ball
101
contains tin (Sn) therein. Though
FIG. 1A
explicitly illustrates the gold layer
8
formed on the wiring layer
2
, it is considered that the gold layer
8
is diffused into the solder ball
101
in a heating step such as a temperature cycle test to be carried out after completion of the semiconductor device, and hence, it is further considered that the gold layer
8
will not exist on the wiring layer
2
after such a heating step is carried out.
As illustrated in
FIG. 1C
, the semiconductor device illustrated in
FIG. 1A
is electrically connected to a printed wiring board
34
through the solder ball
101
.
FIG. 2A
is an enlarged view of the wiring layer
2
and the solder ball
101
, wherein the solder ball
101
is composed of Sn—Pb eutectic solder containing tin
82
at 63% and lead
83
at 37%.
FIG. 2B
is a partially enlarged view of a boundary between the wiring layer
2
and the solder ball
101
. As illustrated in
FIG. 2B
, a Cu—Sn alloy layer
81
having a thickness of 1.75 micrometer to 2.0 micrometer is sandwiched between the wiring layer
2
and the solder ball
101
.
A method of fabricating the conventional semiconductor device illustrated in
FIGS. 1A
to
1
C is explained hereinbelow with reference to
FIGS. 3A
to
3
H and
4
A to
4
H.
FIGS. 3A
to
3
H are partial cross-sectional views of the semiconductor device illustrated in FIG.
1
A.
First, as illustrated in
FIG. 3A
, the wiring layer
2
containing copper therein is formed on an upper surface of the film substrate
3
, and the adhesive layer
31
is formed on a lower surface of the film substrate
3
. The film substrate
3
has a thickness of 12 micrometers, the wiring layer
2
has a thickness of 18 micrometers, and the adhesive layer
31
has a thickness of 10 micrometers. The film substrate
3
is composed of a material having a resistant to a temperature of 250 degrees centigrade or greater, such as polyimide. The adhesive layer
31
is composed of polyimide.
Then, as illustrated in
FIG. 3B
, the wiring layer
2
is patterned into a predetermined pattern.
Then, as illustrated in
FIG. 3C
, the patterned wiring layer
2
and the film substrate
3
are both covered with the resist
32
.
Then, as illustrated in
FIG. 3D
, there is formed the through-hole
4
through the adhesive layer
31
and the wiring layer
2
, for instance, by means of a laser beam gun.
Then, as illustrated in
FIG. 3E
, the through-hole
4
is filled with the metal
5
such as copper or aluminum.
Then, as illustrated in
FIG. 3F
, the metal
5
is covered at a top surface thereof with the gold layer
6
.
Then, as illustrated in
FIG. 3G
, the resist
32
is formed with the land
7
above the wiring layer
2
. In later steps, the solder ball
101
is mounted on the wiring layer
2
in the land
7
.
Then, as illustrated in
FIG. 3H
, the land
7
is covered with the thin gold layer
8
.
Thus, there is completed a tape substrate
93
comprised of the film substrate
3
having the wiring layer
2
formed on the upper surface. Though
FIGS. 3A
to
3
H illustrate only one land
7
, it should be noted that the film substrate
3
is in the form of a sheet, and the film substrate
3
is formed with a plurality of lands
7
in each of which the solder ball
101
is to be mounted in later steps.
A method of mounting solder balls on the wiring layer
2
is explained hereinbelow with reference to
FIGS. 4A
to
4
H.
First, as illustrated in
FIG. 4A
, the tape substrate
93
resulted from the steps illustrated in
FIGS. 3A
to
3
H is placed with the gold layer
6
being upwardly directed. For simplification, the gold layer
6
is not illustrated in FIG.
4
A.
Then, as illustrated in
FIG. 4B
, stiffeners
41
are adhered on the tape substrate
93
at opposite its opposite ends. The stiffeners
41
are composed of copper or stainless, for instance. The stiffeners
41
are used for fixing the tape substrate
93
when the semiconductor chip
1
is mounted onto the tape substrate
93
.
Then, as illustrated in
FIG. 4C
, the semiconductor chip
1
is mounted on the tape substrate
93
, surrounded by the stiffeners
41
. Then, the gold layer
6
is electrically connected to an electrode
12
of the semiconductor chip
1
through a bonding wire (not illustrated). The connection is accomplished by means of a bonding tool, a heater and a ultrasonic wave generator (not illustrated).
Then, as illustrated in
FIG. 4D
, resin
42
is applied between the tape substrate
93
and the semiconductor chip
1
, and then, is cured to thereby reinforce a connection between the tape substrate
93
and the semiconductor chip
1
. The resin
42
is composed of epoxy resin in liquid, for instance.
Then, as illustrated in
FIG. 4E
, a product resulted from the step illustrated in
FIG. 4D
is covered with a cover
43
for the purpose of protection of the semiconductor chip
1
. Then, the cover
43
is sealed under atmospheric pressure. The cover
43
is made of Cu, Al or SiC, for instance.
Electrically conductive adhesive
44
such as Ag paste or Cu paste is coated on a lower surface of the cover
43
. The adhesive
44
is heated, and hence, cured when the cover
43
is sealed.
Then, as illustrated in
FIG. 4F
, the solder balls
101
are absorbed to a positioner
45
, and subsequently, the solder balls
101
are mounted onto the lands
7
formed above the wiring layer
2
. Thereafter, flux (not illustrated) is applied across the solder balls
101
and the lands
7
. Then, the solder balls
7
are caused to reflow to thereby physically connect the solder balls
101
to the lands
7
. Then, the flux is washed out.
Thus, there is completed such a product as illustrated in FIG.
4
G. The product is then subject to a temperature cycle test in order to test performances and resistance to damages.
Then, as illustrated in
FIG. 4H
, the solder balls
101
are caused to reflow to thereby physically connect the solder balls
101
to the printed wiring board
34
. Thus, there is completed a semiconductor device as a final product.
However, the conventional semiconductor device illustrated in
FIGS. 1A
to
1
C is accompani

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