Methods of forming integrated circuitry

Details Methods of forming integrated circuitry Methods of forming integrated circuitry

2001-09-21

2002-08-27

Ho, Hoai V. (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06440817

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming integrated circuitry isolation trenches, to methods of forming integrated circuitry, and to integrated circuitry.
BACKGROUND OF THE INVENTION
Integrated circuitry is typically fabricated on and within semiconductor substrates, such as bulk monocrystalline silicon wafers. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrical components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials. One isolation technique uses trench isolation, whereby trenches are cut into a substrate and are subsequently filled with an insulating material. The insulating material is typically then planarized back to define isolated trenches filled with insulative isolation material. An example prior art construction and its associated problems are described with reference to FIG.
1
. There illustrated is a miconductor wafer fragment
10
comprising a bulk semiconductor wafer
12
having a trench isolation region
14
formed therein. A field effect transistor gate line
16
is formed over substrate
12
, and conventionally comprises a gate dielectric layer, a conductively doped polysilicon region, an overlying high conductive silicide region, an insulative cap and a sidewall spacer which are not specifically designated with numerals. A source/drain diffusion region
18
, also referred to as a junction, extends from proximate gate
16
to isolation trench
14
.
Isolation trench
14
comprises a thermal silicon dioxide lining layer
20
and a greater volume insulating material
21
received therein. An example material
21
is undoped silicon dioxide deposited by high density plasma-enhanced decomposition of tetraethylorthosilicate (PETEOS). An insulative layer
22
is received over the substrate as illustrated. A contact opening
24
is formed through layer
22
and overlies shallow junction region
18
and shallow trench isolation region
14
. In the context of this document, “shallow junction” means a depth less than or equal to about 1000 Angstroms. Unfortunately typically, material
22
also comprises an oxide material (i.e. borophosphosilicate glass) as do materials
21
and
20
within trench isolation region
14
. Accordingly, typical anisotropic etching chemistries used to etch oxide insulative layer
22
also tend to etch oxide materials
20
and
21
of isolation region
14
. This provides the illustrated degree of over-etch and accordingly sidewall exposure of the source/drain junction region
18
. This can undesirably lead to excessive current leakage. If the contact opening etching is sufficient such that it is removed to elevationally lower than junction region
18
, as shown by line
25
, a fatal short to the substrate typically results.
One present prior art solution to the above problem comprises the deposition of a thin Si
x
N
y
O
z
layer prior to deposition of BPSG layer
22
. The BPSG is then etched substantially selectively relative to the Si
x
N
y
O
z
layer using a contact opening mask. Then, the Si
x
N
y
O
z
layer is etched. Yet such Si
x
N
y
O
z
etching can also etch the trench oxides.
As device dimensions in integrated circuitry fabrication continue to get smaller, it is more likely that contact openings will overlie both shallow junction regions and adjacent isolation regions, thus more likely leading to contact leakage at best, and fatal substrate shorts at worst.
The invention was motivated in overcoming this particular problem, although the claims are in no way so limited, with the invention having applicability outside of its motivation in accordance with the accompanying claims as literally worded and appropriately interpreted in accordance with the Doctrine of Equivalents.
SUMMARY
The invention comprises methods of forming integrated circuitry isolation trenches, methods of forming integrated circuitry, and integrated circuitry independent of the method of fabrication. In one implementation, a method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench.
In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials. A first of the materials is received over at least an outermost portion of the sidewall and a second of the materials is received adjacent the first, with the first material being received between the junction isolation region and the second material. A covering insulative material is formed over the trench isolation region and the shallow junction region. A contact opening is etched through the covering insulative material to the shallow junction region and the trench isolation region substantially selective to etch the covering insulative material relative to the first trench isolation material within the trench isolation region.
In one implementation, integrated circuitry includes a semiconductor substrate having a trench isolation region formed therein. The trench isolation region includes laterally opposing sidewalls and a trench base extending between the opposing sidewalls. The trench isolation region includes at least two insulative materials therein. One of the insulative materials is received between the other insulative material and semiconductor material of the semiconductor substrate. The one material is selected from the group consisting of Si
x
N
y
O
z
, Al
2
O
3
, Ta
2
O
5
, nitrides such as silicon nitride and mixtures thereof. An integrated circuit device is received at least partially within the semiconductor substrate proximate the trench isolation region.
Other implementations are contemplated.


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Hong, et al., “A Novel T-Shaped Shallow Trench Isolation Technology”, Jpn. J. Appl. Phys. vol. 40 (2001) pp. 2616-2620, Part 1, No. 4B, Apr. 2001.

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