Method for forming laterally graded deposit-type emitter for bip

Details Method for forming laterally graded deposit-type emitter for bip Method for forming laterally graded deposit-type emitter for bip

1993-06-07

1994-08-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 35, 437 44, 437 59, 148DIG11, 257370, 257591, H01L 21265, H01L 2970

Patent

active

053427947

ABSTRACT:
The present invention provides a BiCMOS integrated circuit with bipolar, NMOS and PMOS transistors. In a bipolar transistor, an emitter buffer is provided to minimize a hot carrier effect. The emitter buffer is implanted using the same mask used for a base link. However, the n-type dopant is implant using a large angle, while the p-type dopant is implanted using a normal implant. A "base" oxide is grown over the implant region. This oxide ultimate isolates the emitter buffer from the polysilicon emitter contact section. Local interconnects are formed using a "dual-gate" technique, in which a tungsten silicide cap layer is formed over polysilicon to short pn junctions in the interconnect.

REFERENCES:
patent: 5100810 (1992-03-01), Yoshimi et al.
patent: 5147809 (1992-09-01), Won et al.
patent: 5198692 (1993-03-01), Momose
patent: 5270227 (1993-12-01), Kameyama et al.

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