Internal clock signal generating circuit permitting rapid...

Details Internal clock signal generating circuit permitting rapid... Internal clock signal generating circuit permitting rapid...

1999-03-22

2002-02-26

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S158000, C327S285000, C375S376000, C331SDIG002

Reexamination Certificate

active

06351169

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for generating a second clock signal in synchronization with a first clock signal and a testing method of the circuit. More particularly, the present invention relates to an internal clock signal generating circuit for generating an internal clock signal in synchronization with an external clock signal in a synchronous semiconductor memory device, a phase comparator, and a testing method of the internal clock signal generating circuit.
2. Description of the Background Art
In a synchronous semiconductor memory device, there is a need to generate an internal clock signal within a chip as desired in order to time the operation of the device to a desired external clock signal. It is difficult, however, to generate such internal clock signal to suit for various types of frequencies, power supply sources, or interfaces.
A DLL (Delayed Line Loop) circuit has thus been used for shifting phases so as to obtain a desired internal clock signal.
A DDR-SDRAM (Double Data Rate SDRAM) is an example of the synchronous semiconductor memory device.
FIG. 42
shows a timing chart for use in illustration of the output timing of DDR-SDRAM. In
FIG. 42
, reference characters extCLK, DQ and intCLKD represent an external clock signal, an output data, and an internal clock signal, respectively.
Referring to
FIG. 42
, data are output corresponding to rising and falling edges of external clock signal extCLK in a DDR-SDRAM. To output data in phase with external clock signal extCLK, internal clock signal intCLKD as a trigger must be generated at least a data output delay time (To) ahead of the output timing.
Now, a configuration of the main portion of semiconductor memory device that includes a conventional internal clock signal generating circuit will be described with reference to FIG.
43
. The conventional semiconductor memory device shown in
FIG. 43
includes a minute delay stage
910
, a phase comparator
930
, a control circuit
950
, an input buffer
2
, an output buffer replica
4
, an input buffer replica
6
, and an output buffer
8
.
Input buffer
2
takes in external clock signal extCLK and outputs a clock signal ORGCLK, which is applied to phase comparator
930
and to minute delay stage
910
as their input signals, respectively. Phase comparator
930
compares the phases of clock signal ORGCLK and of a feedback signal FBCLK output from input buffer replica
6
to determine which signal is advanced in phase.
Phase comparator
930
outputs a down signal ZDOWN that directs to increase the amount of delay to be provided (hereinafter, referred to as “delay amount”), or an up signal ZUP that directs to decrease the delay amount, so as to make these phases substantially synchronized with each other (to establish phase lock). When internal clock signal generating circuit is locked (phase-locked), phase comparator
930
outputs a lock signal ZLOCK at an “L” level.
Minute delay stage
910
includes a plurality of delay elements. Minute delay stage
910
uses that plurality of delay elements to minutely change the delay amount. Control circuit
950
includes a plurality of shift registers provided corresponding to the plurality of delay elements. The plurality of shift registers respond to the output of phase comparator
930
to output a control signal (R(
0
) to R(M−1) in FIG.
43
).
Internal clock signal intCLKD output from minute delay stage
910
controls the output operation of output buffer
8
. Internal clock signal intCLKD passes through output buffer replica
4
and input buffer replica
6
, and is supplied to phase comparator
930
as feedback signal FBCLK. Output buffer replica
4
simulates delay (data output delay time T
0
) at output buffer
8
. Input buffer replica
6
simulates delay (Ti) at input buffer
2
.
For example, suppose that the phase of output data DQ must be delayed by one clock (Tc) relative to external clock signal extCLK. In this case, the delay amount in minute delay stage
910
is fine adjusted to give internal clock signal intCLKD a time delay of (Tc−T
0
) with respect to external clock signal extCLK. (Here, the signal that has passed through output buffer replica
4
is delayed by Tc relative to external clock signal extCLK. Further, the signal having passed through input buffer replica
6
is (Tc+Ti) behind external clock signal extCLK.)
In order to reduce jitter generated in the internal clock signal generating circuit, there is a need to change the delay amount in minute delay stage
910
still more minutely. For example, the above DDR-SDRAM requires a time resolution in unit of 0.1 ns. With the configuration of conventional internal clock signal generating circuit, however, there has been a problem that, as the time resolution is made finer to accommodate to a wider range of frequencies, the number of delay elements inevitably increases, and thus the layout area increases.
In the case where the cycle length Tc to achieve phase lock is 15 ns and data output delay time T
0
is 2 ns, for example, it is necessary to realize the delay of (Tc−Ti−T
0
)=11 ns. Here, if the time resolution in unit of 0.1 ns is required, at least 110 stages (=11 ns/0.1 ns) of delay elements are necessary, and consequently, the number of shift registers to be included in control circuit
950
increases.
If the signal to achieve phase lock is low in frequency, the number of delay elements will increase, which means that considerable amount of time will be required for establishment of phase lock.
Furthermore, as the operating power supply voltage of semiconductor memory device is lowered, there is a need for an internal clock signal generating circuit that can realize a desired delay even with such low voltage.
In addition, in view of the manufacturing cost of the semiconductor memory device per se, judgement on the quality of internal clock signal generating circuit must be performed simply as well as rapidly.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an internal clock signal generating circuit that permits rapid establishment of phase lock and ensures a stable operation, with restricted layout area.
Another object of the present invention is to provide an internal clock signal generating circuit that can realize a desired delay even with a low power supply voltage.
An internal clock signal generating circuit according to an aspect of the present invention is for generating an internal clock signal synchronized in phase with an externally applied external clock signal, and includes: a phase difference detecting circuit for detecting a phase difference between the external clock signal and the internal clock signal; a first delay circuit for delaying the external clock signal for output, which is capable of changing the delay amount by a first time width dependent on the detected phase difference; and a second delay circuit for delaying an output of the first delay circuit for output as an internal clock signal, which is capable of changing the delay amount by a second time width that is larger than the first time width, dependent on the detected phase difference.
Accordingly, a primary advantage of the present invention is that a highly precise internal clock signal generating circuit with small layout area can be realized by utilizing a minute delay stage that can change the delay amount minutely and a delay stage that can change the delay amount by a relatively large amount.
Specifically, the internal clock signal as an object of the detection of phase difference is shifted according to a cycle length to achieve phase lock, whereby an initial lock-in time can be shortened. In addition, the second delay circuit gives a delay according to a cycle length of external clock signal, and thus, the initial lock-in time can further be shortened. After the lock is established, the selected state in the second delay circuit is held, which can suppress generation of jitter.
Further, the phase difference is detected

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