Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

1997-12-30

2002-10-15

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S622000, C438S627000, C438S641000, C257S737000, C216S013000, C427S099300

Reissue Patent

active

RE037882

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device manufacturing method for connecting interconnects to each other in multilayer interconnection substrates, and more particularly to a semiconductor device manufacturing method effective for multichip modules (MCMs).
2. Description of the Related Art
To make semiconductor devices denser and smaller, multichip packages, where more than one semiconductor chip on which integrated circuit elements and discrete semiconductor elements are formed is squeezed in a single package, have recently been in use. With conventional packaging forms, where many DIPs (dual-in-line packages) or plug-in packages are mounted in a printed circuit board, the faster LSIs cannot achieve their best performance. That is, the delay time cannot be shortened because the interconnection runners between chips are too long in terms of signal propagation delay time. To overcome this drawback, high-performance, high-packing-density multichip modules (MCMs) have been developed in which many semiconductor chips are mounted on a single semiconductor substrate such as a ceramic substrate or a silicon substrate, and the interconnection length between semiconductor chips is made very short. Connecting interconnects to each other on a circuit board or a semiconductor substrate is one of the important manufacturing processes for forming semiconductor devices such as ICs or LSIs. In particular, as semiconductor devices are more highly integrated and made smaller, forming multilayer interconnects on a circuit board and efficiently connecting them are indispensable for the formation of high-performance semiconductor devices.
Referring to
FIG. 1
, a method of connecting multilayer interconnects on conventional MCM multilayer interconnection substrates will be explained. For example, on a silicon substrate
1
on whose surface a thermal oxide film of 1000 Å thick is formed, a first layer interconnection
2
with a desired pattern is formed. This interconnection
2
has a multilevel structure of Ti/Cu/Ti comprising of two Ti layers of approximately 600 Å thick and a Cu layer of approximately 3 &mgr;m thick sandwiched between these two Ti layers. The structure is formed by vapor deposition or sputtering techniques.
Then, for example, a polyimide solution is applied to the entire surface of the semiconductor substrate and dried to form a film. Next, by lithography, a contact hole
31
is made in the film. After this, a non-imido film is calcined to form a polyimide film
3
serving as an interlayer insulating film. Then, on the polyimide film
3
, a second layer interconnection
4
of Ti/Cu/Ti, Al, or the like, is formed in a similar manner to the formation of the first layer interconnection
2
. At this time, because the second layer interconnection
4
is also formed in the contact hole
31
, the first layer interconnection
2
and the second layer interconnection
4
are electrically connected to each other in the contact hole
31
. This process is repeated and the interconnects of multilevel layers are connected to one another.
Making the contact hole
31
requires photolithography techniques, etching techniques such as RIE, and such processes as peeling photoresist. Although in the case of polyimide, wet etching can be effected using a choline solution, other organic insulating films must be formed by dry etching. Because the use of wet etching solutions is limited severely, the properties of the films are incompatible with production cost. In addition, as the density of interconnects of the upper layer increases, the upper layer interconnects must be formed on the flat lower-layer surface in a manner that avoids the contact hole in the polyimide film
3
of the lower layer previously formed. This makes it necessary to fill up the contact hole. With this backdrop, the simplification of manufacturing processes is desired.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a method of manufacturing semiconductor devices which facilitate the connection of interconnects and the flattening of interlayer insulating films and are suitable for MCMs.
The foregoing object is accomplished by providing a semiconductor device manufacturing method comprising: the step of forming a lower-layer interconnection on a circuit board on which a plurality of semiconductor chips are mounted; the step of forming a metal pillar on the circuit board so that the pillar may contact with at least the lower-layer interconnection, the metal pillar forming step including the step of effecting screen printing of a metal paste using a screen plate with openings corresponding to desired positions on the lower-layer interconnection and the step of drying and calcining the printed metal paste by heat treatment to form the metal pillar; the step of forming an insulating film covering the lower-layer interconnection and the metal pillar so that the tip of the metal pillar may be exposed; and the step of forming an upper-layer interconnection on the insulating film so that this layer may contact with the exposed tip of the metal pillar.
With this semiconductor device manufacturing method, because a metal pillar to connect interconnects to each other is formed by screen printing in forming multilayer interconnection on a substrate, it is not necessary to make a hole in the interlayer insulating films. Thus, a lithography process and an etching process needed to make a hole can be eliminated. Further, when the tip of the metal pillar is exposed by etching back the interlayer insulating film, the surface of the interlayer insulating film can be flattened. This makes it possible to immediately form the upper-layer interconnects on the flattened surface. In this way, the manufacturing processes can be simplified.


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U.S. patent application Ser. No. 08/075,373, filed Jun. 14, 1993.*
Official Action from Japanese Patent Office in application No. 21738/93, mailing date Jan. 30, 2001, and English language translation.

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