Phase synchronizing circuit in video signal receiver and method

Details Phase synchronizing circuit in video signal receiver and method Phase synchronizing circuit in video signal receiver and method

1989-09-01

1991-02-26

Shepperd, John W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358148, 358153, H04N 504

Patent

active

049965964

ABSTRACT:
A circuit for providing a signal phase locked to a horizontal synchronization signal included in a received video signal includes a first PLL loop (16, 44, 46; 16, 46', 204) and a second PLL or AFC loop (26, 44, 46; 26, 44, 46', 204). The first PPL loop has a plurality of lock ranges. The second PLL or AFC loop, which has an output characteristic with a single S curve, has one lock range large in width. The second PLL or AFC loop is supplied with a horizontal synchronization signal separated in a synchronization separating circuit via a bandpass filter. The first PLL loop is directly supplied with a horizontal synchronization signal extracted in the synchronization separating circuit. The first PLL loop shares a voltage controlled oscillator (46; 46') and a frequency divider (46; 204) with the second PLL loop or AFC loop. This phase synchronizing circuit further includes a circuit (48) for detecting synchronization
on-synchronization of an output of the frequency divider circuit with the horizontal synchronization signal separated/extracted in the synchronization separating circuit, and a switching circuit (42) for activating one of the first PLL loop and the second PLL or AFC loop in response to an output of this synchronization detector circuit.

REFERENCES:
patent: 4069462 (1978-01-01), Dunn
patent: 4228462 (1980-10-01), van Straaten
patent: 4319276 (1982-03-01), Cense et al.
patent: 4488170 (1984-12-01), Nillesen
patent: 4672329 (1987-06-01), Hikawa
patent: 4672447 (1987-06-01), Moring et al.
patent: 4855683 (1989-08-01), Troudet et al.

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