System for store forwarding assigning load and store...

Details System for store forwarding assigning load and store... System for store forwarding assigning load and store...

1999-03-05

2002-02-19

Maung, Zarni (Department: 2154)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C217S023000, C217S074000, C217S074000

Reexamination Certificate

active

06349382

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to the execution of out-of-order load and store instructions in a processor.
BACKGROUND INFORMATION
In order to increase the operating speed of microprocessors, architectures have been designed and implemented that allow for the out-of-order execution of instructions within the microprocessor. An advantage of out-of-order execution of instructions is that it allows load miss latencies to be hidden while useful work is being performed. However, traditionally, load and store instructions have not been executed out of order because of the very nature of their purpose. For example, if a store instruction is scheduled to be executed in program order prior to a load instruction, but the processor executes these two instructions out of order so that the load instruction is executed prior to the store instruction, and these two instructions are referring to the same memory space, there is a likelihood that the load instruction will load incorrect, or old, data since the store instruction was not permitted to complete prior to the load instruction.
Nevertheless, the present invention takes advantage of the foregoing situation to increase the throughput of instructions.
SUMMARY OF THE INVENTION
The present invention increases the throughput of instructions by executing load instructions early in order to hide the latency of the memory subsystem. To ensure that the load instruction receives the correct data, the load address and size are compared to any older store instructions that may have occurred which have not been written to the cache/memory subsystem. Additionally, when a load hit store condition occurs, if the store data is known, it is determined whether this data can be forwarded to the load instruction even if the data has not yet been committed to memory.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 5664215 (1997-09-01), Burgess et al.
patent: 5721857 (1998-02-01), Glew et al.
patent: 5751983 (1998-05-01), Abramson et al.
patent: 5778245 (1998-07-01), Papworth et al.
patent: 5809275 (1998-09-01), Lesartre
patent: 5931957 (1999-08-01), Konigsburg et al.
patent: 6021485 (2000-02-01), Feiste et al.

Affiliated with

Also associated with

Rating

System for store forwarding assigning load and store... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for store forwarding assigning load and store..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for store forwarding assigning load and store... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2972249