Semiconductor memory device and synchronous memory

Details Semiconductor memory device and synchronous memory Semiconductor memory device and synchronous memory

2001-05-16

2002-06-25

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189011

Reexamination Certificate

active

06411564

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device having a data masking function and outputs data based on a plurality of CAS latencies.
The reading and writing of data in a synchronous DRAM is synchronized with a clock signal. A synchronous DRAM having a data masking function and outputs data based on a plurality of CAS latencies has been proposed. Recent portable electronic equipment requires low power consumption devices to lengthen the battery life and prolong operational time. Accordingly, a synchronous DRAM installed in portable electronic equipment must have low power consumption while ensuring the masking of output data.
A synchronous DRAM has an active mode, an idle mode, and a power down mode. During the active mode, data is read and written. During the idle mode, part of an input/output (i/o) circuit is inactivated to decrease power consumption. During the power down mode, most of the i/o circuit is inactivated to decrease power consumption. The power consumption is maximal during the active mode, and the power consumption is minimal during the power down mode. The power consumption during the idle mode is intermediate and corresponds to a level between the power consumption levels of the active mode and the power down mode.
A prior art synchronous DRAM
50
is shown in FIG.
1
. The synchronous DRAM
50
includes a mask signal input circuit
1
, an input control circuit
2
, and a data output circuit
3
. The synchronous DRAM
50
has an output data masking function and outputs data based on CAS latencies.
The mask signal input circuit
1
generates a mask output signal DQMo to mask output data based on a mask signal DQMi provided from an external input terminal IT.
The input control circuit
2
receives a power down signal pd and an active signal ac and controls the activation and inactivation of the mask signal input circuit
1
based on the power down signal pd and the active signal ac.
When the power down signal pd goes low during the power down mode, the input control circuit
2
generates an activation signal X at a low level and sends the low activation signal (inactivation signal) X to the mask signal input circuit
1
. When the active signal ac goes high during the active mode, the input control circuit
2
generates an activation signal X at a high level and sends the high activation signal X to the mask signal input circuit
1
.
When the power down signal pd and the active signal ac are low during the idle mode, the input control circuit
2
generates the low activation signal X and sends the low activation signal X to the mask signal input circuit
1
.
The activation signal X activates the mask signal input circuit
1
. In this state, the mask signal input circuit
1
receives the mask signal DQMi and generates the mask output signal DQMo The mask signal input circuit
1
then sends the mask output signal DQMo to the data output circuit
3
. When inactivated by the low activation signal X, the mask signal input circuit
1
stops providing the mask output signal DQMo to the data output circuit
3
.
The operation of the synchronous DRAM
50
is shown in
FIG. 3
illustrating a data read operation performed when a CAS latency CL is 2.
During the idle mode, the low activation signal X inactivates the mask signal input circuit
1
. Then, when a clock signal CLK goes high at time t
1
, the input control signal
2
receives the high active signal ac and sends the high activation signal X to the mask signal input circuit
1
. This activates the mask signal input circuit
1
.
One cycle of the clock signal CLK after time t
1
, the synchronous DRAM
50
receives a read command READ. Two cycles of the clock signal CLK after time t
1
, the data output circuit
3
outputs read data DQ.
When masking the data DQ output based on the first read command READ, the mask signal DQMi received by the mask signal input circuit
1
goes high at the same time as when the synchronous DRAM
50
receives the read command READ. Afterward, the mask signal input circuit
1
sends the mask output signal DQMo to the data output circuit
3
. Based on the mask output signal DQMo, the data output circuit
3
masks the read data DQ.
A latency LQRM of the mask signal DQMi is normally set to a value of 2 or greater. Thus, the timing at which the mask signal DQMi is provided to the mask signal input circuit
1
is one or more clock signal CLK cycles prior to the timing at which the output of the data DQ is started.
During the idle mode, the mask signal input circuit
1
is inactivated regardless of the level of the mask signal DQMi, Thus, the power consumption is decreased during the idle mode.
During the active mode, the mask signal input circuit
1
is activated. In this state, the mask signal input circuit
1
receives the mask signal DQMi and generates the mask output signal DQMo based on the mask signal DQMi. Further, the data output circuit
3
receives the mask output signal DQMo and masks the data DQ output based on the first read command READ.
During the power down mode, the input control circuit
2
provides the mask signal input circuit
1
with the low activation signal X based on the high power down signal pd. The low activation signal X inactivates the mask signal input circuit
1
, and thus decreases power consumption.
In the synchronous DRAM
50
, the CAS latency is switched between the values of one and two or greater. The operation performed, when the CAS latency is 1, is shown in FIG.
4
.
During the idle mode, the low activation signal X inactivates the mask signal input circuit
1
. Then, when the clock signal CLK goes high at time t
1
, the input control signal
2
receives the high active signal ac and sends the activation signal X to the mask signal input circuit
1
.
One cycle of the clock signal CLK after time t
1
, the synchronous DRAM
50
receives the read command READ. Afterward, the data output circuit
3
outputs the data DQ within one cycle of the clock signal CLK after time t
1
.
Since the latency LRQM is 2, to mask the data DQ output based on the first read command READ, the mask signal input circuit
1
must receive the mask signal DQMi at the same time as when the active mode starts.
However, the input control circuit
2
generates the activation signal X after receiving the active signal ac and activates the mask signal input circuit
1
with the activation signal X. Thus, the mask signal input circuit
1
cannot generate the mask output signal DQMo at the same time as when the input control circuit
2
receives the active signal ac. As a result, the data DQ that is output based on the first read command READ is not masked when the CAS latency CL is 1.
FIG. 2
shows a synchronous DRAM
50
A proposed to solve this problem. The synchronous DRAM
50
A includes an input control circuit
2
A receiving only the power down signal pd. The input control circuit
2
A generates the low activation signal X when the power down signal pd goes high.
In this case, the mask signal input circuit
1
is activated during the idle mode. Thus, the mask signal input circuit
1
acquires the mask signal DQMi at the same time as when the active mode is started. As a result, the data DQ output based on the first read command READ is masked even if the CAS latency is 1 and the latency LRQM is 2.
However, when the mask signal DQMi is simultaneously provided to, for example, a plurality of banks or chips, the mask signal input circuits
1
in the banks or chips are activated during the idle mode. Thus, the mask signal DQMi provided to each mask signal input circuit
1
increases the power consumed by the mask signal input circuit
1
and the circuit in the next stage.
Further, the mask signal input circuit
1
is activated during the idle mode even when the CAS latency is set at a value of 2 or greater. This increases power consumption.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device performing data masking without increasi

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