Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
1995-07-18
2002-02-26
Teska, Kevin J. (Department: 2825)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C710S120000
Reexamination Certificate
active
06351725
ABSTRACT:
The invention relates to interface apparatus for connection between a data handling device and a data communication medium to enable data to be transferred between the device and the medium.
A typical example of such interface apparatus is an adaptor card for connection between a data processor such as a PC and a communication network such as a FDDI network.
Currently there are three basic architectures for such interface apparatus. In the Bus Master architecture, data is transferred directly from the adapter card to the PC memory using direct memory access (DMA) operations. While this system is very fast it suffers from the disadvantage that once receive frames are copied into the PC they may have to be transferred elsewhere (typically by the PC copying the frame byte by byte) once the receive data has been examined. Much of the copying may just be necessary to shift the data so that a particular sequence of bytes within the frame starts on a word or long word boundary within memory.
In the Shared RAM architecture, the adapter card contains an area of RAM that is visible to the main PC processor. Received frames are placed into this RAM on the adapter card and then copied from the RAM on the adapter card to the main PC memory by the PC's processor.
In the Programmed Input Output (PIO) approach, the adapter card is sent the frame through a fixed size (typically 8, 16 or 32 bit) I/0 location under CPU Control. These transfers, being driven by the host processor, suffer performance limitations.
In accordance with the present invention, interface apparatus for connection between a data handling device and a data communication medium to enable data to be transferred between the device and the medium comprises a data alignment device coupled in use to the data handling device; a memory coupled, for data transfer, to the data alignment device, the memory including a number of substantially identical subsidiary, First In-First Out (FIFO) memories arranged in parallel, the number of subsidiary memories being chosen such that their overall width is at least equal to the longest length of data to be transferred between the memory and the alignment device in a single transfer step and the width of each subsidiary memory being equal to the shortest length of data to be transferred between the memory and the alignment device in a single transfer step; the data alignment device having a number of first ports, one connected to each of the subsidiary FIFOs and a corresponding number of second ports connected in use to the data handling device, and means for connecting any first port to any second port; and control means for controlling operation of the data alignment device such that in any transfer step, data having a length corresponding to an integer multiple of the said shortest length of data can be transferred between the memory and the second ports of the data alignment device with the order of data within the length of data being determined by the connections between the first and second ports of the data alignment device.
The memory may be used as a “transmit” memory to enable data to be transferred from the data handling device to the data communication medium or as a “receive” memory to handle data transfer from the medium to the data handling device. In practice, the interface apparatus will typically comprise two such memories, a transmit memory and a receive memory with respective data alignment devices.
The invention enables data of varying length to be sent to or read from the memory without the need to load large blocks of data into another memory of for example a CPU to enable it to be examined. Thus, where the data handling device comprises a PC, this will not have to copy data to align the data correctly in memory for a particular computer protocol, data (even within the same frame) can be copied between the PC and the interface apparatus either by the PC processor or by supporting DMA circuits, and the overhead on the PC's CPU is minimised for each frame transferred. Most importantly, the data transfer is not limited to a fixed size as with PIO. Instead varying integer multiples of the shortest length of data (1 byte) can be transferred.
Typically, the subsidiary FIFOs may be implemented as RAM with extra control circuits, as dedicated FIFO devices, or in VRAM.
In some cases, there may be a common data alignment device for both the transmit and receive memories since, where the data handling device is connected to the apparatus via a computer bus, such a bus cannot normally transmit and receive simultaneously. However, separate data alignment devices could be provided for each of the receive and transmit memories.
Preferably, one or more additional memories such as FIFOs are provided in parallel with the or each of the receive and transmit memories. This allows status information such as start and end of frame information together with any error indications in receive frames to be kept adjacent to the correct data.
The data handling device can comprise a computer such as a PC but also any other high speed peripheral device. Furthermore, the data handling device could be defined by both a processor (CPU) and a direct memory access (DMA) device with the CPU handling certain parts of the data transfer and the DMA the other parts. In particular, where the data defines a frame, the CPU could take part in the transfer of the frame header while the DMA device can control the transfer of information content.
The communication medium can be any kind of medium such as a token ring but the invention is particularly suited for use with a FDDI network.
REFERENCES:
patent: 5168561 (1992-12-01), Vo
patent: 5299313 (1994-03-01), Petersen et al.
patent: 5305317 (1994-04-01), Szczepanek
patent: 0290172 (1988-11-01), None
patent: 88/03292 (1988-05-01), None
IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul., 1986, New York, pp. 864-868, “Hardware-Assisted Byte-Alignment for High-Speed Digital Communications Porcessors.”
Suggett Adrian Michael
Willis Trevor Edward
Madge Networks Limited
Siek Vuthe
Sughrue Mion Zinn Macpeak & Seas, PLLC
Teska Kevin J.
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