Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2000-10-12
2002-02-05
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S132000, C438S150000, C438S156000, 43, 43, 43, C148S030000
Reexamination Certificate
active
06344374
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to device isolation techniques. More particularly, it relates to a novel method of forming an isolation region in a silicon-containing substrate.
2. Description of the Related Arts
Device isolation techniques play an important role in the design and performance of highly integrated semiconductor circuits by electrically isolating regions and devices therein from adjacent devices and regions. Moreover, as the degree of integration in semiconductor circuits increases, there is a concomitant need to develop techniques for forming isolation regions which are free of defects and can be scaled to provide isolation regions having smaller dimensions, but without sacrificing the isolation capability of the regions.
One widely used and relatively simple technique for providing device isolation is typically referred to as local oxidation of silicon (LOCOS). Unfortunately, this technique has a number of disadvantages because it typically includes the formation of bird's beak oxide extensions, induces lattice stress which can lead to the formation of crystal defects in semiconductor substrates, and causes redistribution of channel-stop dopants. As will be understood by those skilled in the art, these disadvantages typically cause a reduction in the lateral area available for active devices, and degrade the reliability and performance of devices formed in adjacent active regions.
Another method which may be considered an improvement over the LOCOS method is typically referred to as the shallow trench isolation (STI) method. In the STI method, a device isolation region is established by selectively etching a semiconductor substrate to form trenches therein and then filling the trenches with an electrically insulating region (e.g., oxide). A chemical etching and/or chemical-mechanical polishing (CMP) step can then be performed to planarize the electrically insulating region to be level with the surface of the substrate. Because the STI method typically does not include a lengthy thermal oxidation step as typically required by the LOCOS method, many of the disadvantages of the LOCOS method can be eliminated to some degree. However, as will be understood by those skilled in the art, the STI method may be prone to a “dishing” phenomenon which can degrade the isolation characteristics of trench isolation regions. In addition, the trench etching causes damage to the semiconductor substrate.
SUMMARY OF THE INVENTION
In view of the above mentioned shortcomings, an object of the present invention is to provide a new isolation method in addition to the traditional STI and LOCOS methods.
Another object of the invention is to provide a new isolation method, by which the formation of bird's beak oxide extensions in the LOCOS method can be eliminated.
A further object of the invention is to provide a new isolation method, by which the disadvantages of the STI method, such as the “dishing” phenomenon and the etching damage to substrate, can be obviated.
To attain the above and other objects, the present invention provides a method of forming an isolation region in a silicon-containing substrate, which includes the steps of: (a) forming a mask layer on the silicon-containing substrate; (b) forming a window in the mask layer to expose the isolation area to be formed in the substrate; (c) forming an oxygen-containing region in the substrate by introducing oxygen-containing ions through the window in the mask layer; and (d) thermally treating the oxygen-containing region to form a non-buried silicon oxide insulator which serves as an isolation region for isolating electronic devices.
Optionally, a barrier layer is provided on the substrate surface before forming the mask layer. The barrier layer can be used as an implanting barrier when introducing the oxygen-containing ions into the substrate.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description which makes reference to the accompanying drawings.
REFERENCES:
patent: 4159915 (1979-07-01), Anantha et al.
patent: 4214315 (1980-07-01), Anantha et al.
patent: 5272098 (1993-12-01), Smayling et al.
patent: 5679601 (1997-10-01), Wu
Intellectual Property Solutions, P.L.L.C.
Vanguard International Semiconductor Corporation
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