Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
1999-09-30
2002-11-05
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C710S061000
Reexamination Certificate
active
06477637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and apparatus for data processing in general, and in particular to a method and apparatus for transporting access requests within a data processing system. Still more particularly, the present invention relates to a method and apparatus for queuing and transporting store requests between functional units within a processor.
2. Description of the Prior Art
Designers of modern state-of-the-art processors are continually attempting to enhance performance aspects of such processors. One technique for enhancing data processing efficiency is the achievement of shorter cycle times and a lower cycles-per-instruction ratio by issuing multiple instructions concurrently. In conjunction, separate execution units that can operate concurrently may be utilized to execute issued instructions. For example, some superscalar processors employ pipelined branch, fixed-point, and floating-point executions units to execute multiple instructions concurrently. As a result of the concurrent issuance and execution of multiple instructions, instruction execution performance is increased.
In addition, processor designers are faced with the challenge of constructing efficient means for sending pipeline commands, request or instructions, between various functional units within a processor. Because multiple cycles are required to transport a command between two functional units within a large processor, it is important that the transport protocol can maximize the rate at which commands can be sent, even with added transport latency that may exist between the two functional units. This is because even with multiple execution units, the performance of a processor still depends upon the rate at which instructions, commands, and requests can be transported between functional units. Thus, it should be apparent that a need exists for an improved method and apparatus for transporting instructions, commands, or requests between functional units within a processor such that transport delay among functional units is minimized.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a data processing system includes a data dispatching unit, a data receiving unit, and a segmented data pipeline along with a segmented feedback line coupled between the data dispatching unit and the data receiving unit. Having multiple latches interconnected between segments, the segmented data pipeline systolically transfers data from the data dispatching unit to the data receiving unit. The segmented feedback line has multiple control latches interconnected between segments. Each of the control latches sends a control signal to a respective one of the latches in the segmented instruction pipeline to forward data to a next segment within the segmented data pipeline.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Arimilli Ravi Kumar
Cargnoni Robert Alan
Guthrie Guy Lynn
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