Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-10-27
2002-11-19
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S068000, C345S041000, C345S042000
Reexamination Certificate
active
06483487
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display and method of driving the same.
A plasma display (to be referred to as a PDP hereinafter) performs display on the basis of discharge emission, and hence can have a low-profile structure. In addition, the PDP can have a high display contrast and relatively large screen without any flicker. The PDP is of a spontaneous emission type having a high response speed and can perform multicolor emission by using phosphors. Owing to these characteristics, the PDP has recently been used in many fields, e.g., the field of display apparatuses associated with computers and the field of color image display.
Such PDPs are roughly classified, according to operation schemes, into AC discharge type PDPs in which electrodes are coated with dielectric layers and indirectly operated in an AC discharge state and DC discharge type PDPs in which electrodes are exposed in a discharge space and operated in a DC discharge state.
The AC discharge type PDPs are classified, according to driving schemes, into memory-driven PDPs designed to cause discharge by using the display information stored in memories mounted on panels themselves and refresh PDPs designed to repeatedly read out display information from external memories and output the information to panels so as to perform discharge display. The memory-driven PDPs suited for large-capacity display have currently become mainstream.
The brightness of the PDP is proportional to the number of times of discharge on the panel. In the refresh PDP, therefore, as the display capacity increases, the number of times of discharge decreases, resulting in a reduction in brightness. For this reason, the refresh operation scheme is used for PDPs with small display capacities.
FIG. 13
shows one display cell of a general AC discharge memory-driven PDP.
Referring to
FIG. 13
, a display cell
1
has insulating substrates
11
and
12
which are front and rear surfaces made of glass. Components such as electrodes are formed between the insulating substrates
11
and
12
. More specifically, a scan electrode
13
and sustain electrode
14
which are made of transparent conductive films are selectively formed under the insulating substrate
11
, and trace electrodes
15
and
16
made of metal conductive films are formed under the scan electrode
13
and sustain electrode
14
to reduce the resistances of the scan electrode
13
and sustain electrode
14
. The scan electrode
13
, sustain electrode
14
, and trace electrodes
15
and
16
are covered with a transparent dielectric layer
20
. A protective layer
21
made of a magnesium oxide is formed on the entire lower surface of the dielectric layer
20
to protect the dielectric layer
20
against discharge caused by a discharge gas.
A discharge gas space
18
filled with a discharge gas such as helium, neon, xenon, or a gas mixture thereof is formed under the protective layer
21
. A phosphor
19
for converting ultraviolet rays produced by discharge caused by the discharge gas into visible light
23
is formed under the discharge gas space
18
. A dielectric layer
22
is formed under the phosphor
19
. A data electrode
17
is formed between the dielectric layer
22
and the insulating substrate
12
.
Note that the scan electrode
13
in
FIG. 13
corresponds to each of reference symbols Sc and Sc
1
to Scm in each drawing to be described later. The sustain electrode
14
in
FIG. 13
corresponds to each of reference symbols Su and Su
1
to Sum in each drawing to be described later. The data electrode
17
in
FIG. 13
corresponds to each of reference symbols Di and D
1
to Dn in each drawing to be described later.
FIG. 14
shows the schematic arrangement of an AC discharge memory-driven PDP.
Referring to
FIG. 14
, the PDP is comprised of a panel
2
made up of display cells
1
, each shown in
FIG. 13
, arranged in the form of a matrix, control circuit
3
for controlling the display operation of the panel
2
, scan driver
4
for driving the scan electrodes Sc
1
to Scm of the respective display cells
1
, sustain driver
5
for driving the sustain electrodes Su
1
to Sum of the respective display cells
1
, and address driver
6
for driving the data electrodes D
1
to Dn of the respective display cells
1
.
The control circuit
3
is constituted by a frame memory
31
for storing display data, signal processing circuit
32
for performing signal processing and outputting the resultant data to the address driver
6
, and driver control circuit
33
for controlling the scan driver
4
and sustain driver
5
.
The panel
2
is a dot matrix display panel having the display cells
1
arranged on m rows and n columns. This panel has row electrodes constituted by the scan electrodes Sc
1
to Scm and sustain electrodes Su
1
to Sum which are parallel to each other, and column electrodes constituted by the data electrodes D
1
to Dn crossing the electrodes Sc
1
to Scm and Su
1
to Sum at right angles. The display cells
1
are formed at the intersections of the row and column electrodes.
The scan electrode driving waveforms generated by the scan driver
4
are applied to the scan electrodes Sc
1
to Scm. The sustain electrode driving waveforms generated by the sustain driver
5
are applied to the sustain electrodes Su
1
to Sum. The data electrode driving waveforms generated by the address driver
6
are applied to the data electrodes D
1
to Dn.
The signal processing circuit
32
of the control circuit
3
generates control signals for the scan driver
4
and sustain driver
5
on the basis of external fundamental signals (a vertical sync signal Vsync, horizontal sync signal Hsync, clock signal Clock, and data sync signal DATA). These control signals are supplied to the respective drivers
4
and
5
through the driver control circuit
33
. The data to be displayed on the display cell
1
is extracted from the frame memory
31
by the signal processing circuit
32
in synchronism with the clock signal Clock and data sync signal DATA, and is supplied to the display cell
1
through the address driver
6
.
The write discharge operation of the display cell
1
having the above arrangement will be described next.
So-called write discharge is caused in the display cell
1
in which a pulse voltage exceeding a discharge threshold is applied between the scan electrode
13
and the data electrode
17
. At this time, since both the electrodes
13
and
17
are covered with the insulating layers, positive and negative charges are stored on the surfaces of the dielectric layers
20
and
22
on the two sides to generate wall charges. These wall charges decrease the effective voltage in the cell. As a consequence, the discharge in the cell is terminated within a short period of time.
In sustain discharge operation dominating emission display, a sustain pulse having the same polarity as that of the voltage based on the wall charges is applied between the adjacent scan electrode
13
and sustain electrode
14
. With this operation, since the sustain pulse voltage is superimposed on the voltage based on the wall charges, even if the sustain pulse voltage is low, the resultant voltage exceeds the discharge threshold between the scan electrode
13
and the sustain electrode
14
. As a consequence, discharge occurs. If, therefore, sustain pulses are kept alternately applied to the scan electrode
13
and sustain electrode
14
, the discharge between the electrodes can be maintained.
Sustain discharge can be quickly stopped by applying a low-voltage pulse having a large pulse width which cancels out the voltage based on wall charges or erase pulse having a small pulse width and a voltage near the sustain pulse voltage to the scan electrode
13
or sustain electrode
14
.
FIGS. 15A
to
15
F show the first conventional example of the driving operation of the AC discharge memory-driven PDP in FIG.
14
. In the first conventional example, write discharge and sustain discharge are caused at different timings.
FIGS. 15A
shows a sustain pulse Wc applied to the sustai
Choate Hall & Stewart
Chow Dennis-Doon
Nelson Alecia D.
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