Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-02-06
2002-10-22
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C324S758010
Reexamination Certificate
active
06469532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to methods for testing semiconductor circuitry for operability. More particularly, the invention pertains to interconnects and methods for fabrication thereof which are suitable for testing circuits of a bare die or multiple dice of an unsingulated wafer substantially without or with minimal “crosstalk” or other electrical interference.
2. State of the Art
In the current state of the art, bare semiconductor dice are finding increased use in constructions of multi-chip-modules (MCM) having a large number of dice. MCM are particularly vulnerable to semiconductor die defects, because if only one of the multiple, e.g., 10-30 or more dice, is defective, the module is considered defective and is generally discarded at considerable monetary loss. Thus, for example, if the individual die has a mean acceptance rate of 98.0 percent, a series of MCM, each with 25 dice, would have a predicted overall acceptance rate of about 70 percent, which is unacceptable from the standpoint of production cost and resulting price to the customer. A MCM having a greater number of dice will have a lower acceptance rate.
In view of requirements for greater reliability of increasingly complex integrated circuits such as are included in (MCM), semiconductor manufacturers now supply bare, i.e., unencapsulated, dice which have been pretested for operability in accordance with a set of specifications. Dice meeting the manufacturer's test specifications are certified as known-good-die (KGD).
Considerable effort has been expended to develop test equipment and methods for accurately testing an individual or discrete semiconductor die to enable KGD certification. For example, apparatus for conducting burn-in tests for a discrete die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., both patents assigned to Micron Technology, Inc. Other test apparatus for a discrete die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., both assigned to Texas Instruments, and in U.S. Pat. No. 5,451,165 to Cearley-Cabbiness et al., U.S. Pat. No. 5,475,317 to Smith, U.S. Pat. No. 5,572,140 to Lim et al., 5,406,210 to Pedder, U.S. Pat. No. 5,378,981 to Higgins III, U.S. Pat. No. 5,402,077 to Agahdel et al., and U.S. Pat. No. 5,565,767 to Yoshimizu et al.
In order to test a discrete semiconductor die, temporary electrical connections must be made between the bond pads on a bare semiconductor die and the external test circuitry of the test apparatus using the bond pads of the die to provide the connection points for testing the integrated circuit of the die. Bond pads on semiconductor dice are typically formed of layers of various metals, such as aluminum, copper, nickel, gold, alloys thereof, or solder of various metallurgies. The bond pads of semiconductor die for connections thereto are typically formed in a flat, planar configuration or as a raised bump.
The test apparatus for discrete semiconductor dice use various techniques for making a nonpermanent connection to the bond pads of a semiconductor die. The Wood et al. patent shows a die contact member that uses nonbonded TAB (tape automated bonding) technology. The Elder et al. apparatus uses a flexible connection member having an arrangement of probe bumps or members for temporary contact with the wire bond pads of the semiconductor die. The Malhi et al. apparatus uses an arrangement of cantilevered probe tips to contact the bond pads of the semiconductor die.
In U.S. Pat. No. 5,326,428 to Farnworth et al., a method for fabricating a probe is disclosed which is used for nonpermanent test contact with a bond pad on a semiconductor die.
U.S. Pat. No. 5,517,752 to Sakata et al. discloses a probe provided on a pressure-connector terminal used for TAB and COG connection to the bond pads of the semiconductor die.
One disadvantage of prior art test fixtures for semiconductor die testing, such as probe cards, is that their use often results in electronic interference, i.e., “crosstalk” between fixture leads, even at what are considered to be moderate frequencies for testing the die. This problem essentially precludes the application of existing test fixtures such as probe cards to the simultaneous testing of multiple bare semiconductor dice. Another problem in testing multiple semiconductor dice in wafer form is that of misalignment and disconnection of contact members from bond pads of dice being tested resulting from a probe card and a wafer containing the dice, each having different coefficients of thermal expansion (CTE). Thus, each discrete semiconductor die of a wafer or MCM must be separately tested, one at a time, resulting in much greater testing time and expense than are desirable. The need for apparatus and methods enabling rapid testing of multiple bare semiconductor dice is evident.
BRIEF SUMMARY OF THE INVENTION
The present invention comprises a shielded raised contact member for nonpermanent connection to a semiconductor die or dice for testing thereof. The invention also comprises methods for fabricating the contact member and interconnects using such fabrication methods. The traces connected to the raised contact members on the interconnect are coaxially covered with a metal layer and an intervening insulation layer such as silicon dioxide. The invention also encompasses an improved multiple contact test device, e.g., probe card for testing a singulated semiconductor die or a plurality of semiconductor dice, for example, in wafer form. The metal shielding substantially prevents or minimizes interference or “crosstalk” which has, in the past, prevented simultaneous, high-speed testing of multiple semiconductor dice for KGD certification. In a preferred embodiment, the substrate of the test device is formed of the same semiconductive material as the die(s) under test, e.g., silicon, whereby the CTE are matched. Misalignment of contact members with bond pads of the semiconductor die or dice during the connection step and disconnection of contact members of the interconnect from the bond pads during the test (due to temperature change of the probe card and die(s)) is avoided. The present invention further provides for the control of the depth of penetration of contact members with respect to the bond pads of the semiconductor device or the deformation of the bond pads during the connection step.
REFERENCES:
patent: 4899107 (1990-02-01), Corbett et al.
patent: 4937653 (1990-06-01), Blonder et al.
patent: 5073117 (1991-12-01), Malhi et al.
patent: 5123850 (1992-06-01), Elder et al.
patent: 5177439 (1993-01-01), Liu et al.
patent: 5302891 (1994-04-01), Wood et al.
patent: 5323035 (1994-06-01), Leedy
patent: 5326428 (1994-07-01), Farnworth et al.
patent: 5378981 (1995-01-01), Higgins
patent: 5402077 (1995-03-01), Agahdel et al.
patent: 5406210 (1995-04-01), Pedder
patent: 5451165 (1995-09-01), Cearley-Cabbiness et al.
patent: 5469072 (1995-11-01), Williams et al.
patent: 5475317 (1995-12-01), Smith
patent: 5478779 (1995-12-01), Akram
patent: 5483741 (1996-01-01), Akram et al.
patent: 5506514 (1996-04-01), Difrancesco
patent: 5517752 (1996-05-01), Sakata et al.
patent: 5565767 (1996-10-01), Yoshimizu et al.
patent: 5572140 (1996-11-01), Lim et al.
patent: 5678301 (1997-10-01), Gochnour et al.
patent: 6175242 (2001-01-01), Akram et al.
Akram Salman
Hembree David R.
Wood Alan G.
Le N.
Micro)n Technology, Inc.
Sundaram T. R.
TraskBritt
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