Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2001-03-09
2002-06-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S118000, C438S106000, C438S455000, C438S459000
Reexamination Certificate
active
06406942
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flip chip type semiconductor device wherein semiconductor chips are mounted on a multilayer wiring substrate and a method for manufacturing the same. Particularly, the present invention relates to a flip chip type semiconductor device which can be manufactured at low cost and set the wiring pattern pitch of the multilayer wiring substrate at 10 &mgr;m or less and a manufacturing method thereof.
2. Description of the Related Art
FIGS. 1A and 1B
show a conventional flip chip type semiconductor device
101
. In the flip chip type semiconductor device shown in
FIG. 1A
, external terminals (not shown) are formed in the peripheral sections of a semiconductor chip
102
or an active region on the semiconductor chip
102
in an area array arrangement. Protruding bumps
103
are formed out of a metal material such as a solder, Au, an Sn—Ag alloy or the like on the external terminals, respectively.
This flip chip type semiconductor device
101
is mounted on a multilayer wiring mounted substrate
104
as shown in FIG.
1
B. Electrode pads are formed on the multilayer wiring mounted substrate
104
to have the same pattern as the bump array pattern of the flip chip type semiconductor device
101
. An end user mounts the flip chip type semiconductor device
101
on the multilayer wiring mounted substrate
104
while the bumps
103
of the device
101
aligned to the electrode pads of the multilayer wiring mounted substrate
104
, respectively. If a solder is used as a bump material, the flip chip type semiconductor device
101
is mounted on the multilayer wiring mounted substrate
104
by an IR reflow step using flux.
However, the conventional flip chip type semiconductor device
101
has a disadvantage in that after mounting the semiconductor device
101
on the multilayer wiring mounted substrate
104
, a temperature cycle characteristic, in particular, among mounting reliability factors deteriorates due to mismatch in the linear expansion coefficient between the multilayer wiring mounted substrate
104
and the flip chip type semiconductor device
101
. To solve this disadvantage, the following measures have been conventionally taken.
First, with a view to making the linear expansion coefficient of the multilayer wiring mounted substrate
104
closer to that of silicon, a ceramic material such as AlN, mullite or glass ceramic, which is expensive as a material, has been used to minimize mismatch in the linear expansion coefficient, to thereby enhance mounting reliability. Although this attempt was effective for enhancing mounting reliability, it is applicable only to high-end super computers, large computers or the like because an expensive ceramic material is used for the multilayer wiring substrate.
In recent years, there is proposed a technique capable of enhancing mounting reliability by mounting a flip chip semiconductor device while arranging an under-fill resin between a multilayer wiring substrate made of an organic material, which is inexpensive and has a high linear expansion coefficient, and a semiconductor chip. By arranging the under-fill resin between the semiconductor chip and the multilayer wiring substrate made of an organic material, it is possible to disperse a shearing force exerted on a bump connection portion existing between the semiconductor chip and the multilayer wiring substrate made of an organic material and to thereby enhance mounting reliability. In this way, it is possible to employ a multilayer wiring substrate made of an inexpensive organic material by interposing an under-fill resin between the semiconductor chip and the multilayer wiring substrate made of the organic material.
Nevertheless, with this conventional technique, if voids exist in the under-fill resin, or the bonding characteristic at the interface between the under-fill resin and the semiconductor chip and the interface between the under-fill resin and the multilayer wiring substrate made of an organic material are not good, a separation of the bonding portion occurs at the interfaces in a step of reflow absorbing the moisture to a product to thereby disadvantageously make the product defective. For that reason, the above-stated conventional technique does not ensure reducing the cost of a flip chip type semiconductor device.
Further, a multilayer wiring substrate referred to as a buildup substrate is normally employed for a multilayer wiring substrate made of an organic material for a flip chip type semiconductor device because of the shortest pitch of a bump array pattern and the number of pins. A method of manufacturing this buildup substrate will be described with reference to
FIGS. 2A
to
2
F.
First, as shown in
FIG. 2A
, a Cu foil layer
111
having a predetermined thickness of 10 to 40 &mgr;m is bonded to each surface of a core substrate
110
made of an insulating glass epoxy material and patterning is conducted to the Cu foil layer
111
. After forming holes in the core substrate
110
by drilling or the like, the through holes are subjected to a plating processing, thereby forming penetrating through hole sections
112
to electrically connect the Cu foil layers
111
on the both surfaces of the core substrate
110
to each other. In that case, an insulating resin layer
113
is usually filled in the penetrating through hole section
112
in light of the process stability of later steps and the quality stability of the substrate.
Next, as shown in
FIG. 2B
, an insulating resin layer
114
is arranged on the Cu wiring pattern existing on the front and rear surfaces of the core substrate
110
, respectively and openings
115
are thereby formed at predetermined positions of the insulating resin layer
114
by a chemical etching method utilizing a photoresist technique, a laser processing technique or the like.
Then, as shown in
FIG. 2C
, metal thin layers
16
are formed by sputtering metal such as Ti or Cu, or by electroless plating Cu on the insulating resin layer
114
so as to secure the electrical connection between a feed layer for electrolytic plating of Cu and the Cu wiring pattern on the core substrate.
Thereafter, as shown in
FIG. 2D
, to form a wiring pattern by electrolytic plating of Cu, a photo-resist
117
or a dry film having a thickness of about 20 to 40 &mgr;m is arranged on each surface of the metal thin film layer
116
, and exposure and development processing is conducted thereto.
As shown in
FIG. 2E
, using the exposed metal thin film layers
116
as feed layers, an electrolytic plating of Cu is conducted to thereby form wiring pattern sections
118
.
Then, as shown in
FIG. 2F
, after separating the photoresists
117
or dry films, using the wiring pattern sections
118
as a mask, the metal thin film layers
116
are removed by wet etching and the wiring pattern sections
118
are made electrically independent.
By repeating the steps shown in
FIGS. 2B
to
2
F, it is possible to form a multilayer wiring substrate having six or eight metal layers according to necessity.
However, in the above-stated buildup substrate manufacturing method, it is necessary to employ photoresists
117
or dry films each having a thickness of about 20 to 40 &mgr;m so as to secure the thickness of the buildup layer wiring pattern sections in view of the relax of a stress caused by the difference in the thermal expansion coefficient between the core substrate
110
and the buildup substrate and the reliability of the multilayer wiring substrate such as the reliability of connection via hole sections and the like. Due to this, it is necessary to use photoresists
117
or dry films each having a thickness of 20 to 40 &mgr;m. Pattern formation characteristic which can be realized, is only about 30 &mgr;m at the shortest pitch in exposure and development steps accordingly. As a result, the wiring pattern pitch becomes 30 &mgr;m at the shortest and it is impossible to promote making the multilayer wiring substrate high in density and the outer shape of the substrate small in size. Further
Lattin Christopher
NEC Corporation
Niebling John F.
Young & Thompson
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