Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-04-29
2002-06-04
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000, C345S068000, C315S169400
Reexamination Certificate
active
06400342
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. HEI9(1997)-335288, filed on Dec. 5, 1997 whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving an AC surface discharge plasma display panel (PDP).
For realizing display of a full motion picture like a television picture on a high-definition AC PDP, it is desirable to adopt a driving method which employs a so-call erase addressing, because the erase addressing is superior in speed to a write addressing.
2. Description of Related Art
Three-electrode AC surface discharge PDPs have become commercial as color display devices. The three-electrode AC surface discharge PDPs have pairs of main electrodes for sustaining light emission on individual rows and address electrodes on individual columns for matrix display. Since they are of AC-driven type, a memory function of a dielectric layer covering the main electrodes is utilized for display. That is, addressing is carried out to produce a charged state according to the content of display, and then a sustain voltage Vs of an alternating polarity for sustaining light emission is applied across all the main electrodes. Thereby, only in cells in which wall charge exists, an effective voltage Veff exceeds a firing voltage Vf to generate surface discharges along a substrate.
For displaying images in time sequence, uniformly charged state needs to be created on a whole screen during a period from the end of sustaining light emission for one image to the addressing for the next image in order to prevent disturbance of display. Accordingly, in the case of the erase addressing to erase wall charge from cells which need not be lighted, the entire screen must be uniformly charged prior to the addressing.
Conventionally, the wall charge is produced by applying a write voltage exceeding the firing voltage Vf simultaneously to all the pairs of main electrodes defining the individual rows on the screen. If the polarity of the write voltage is so chosen that a remaining wall charge lowers the effective voltage Veff, a discharge is selectively generated to produce wall charge only in cells in which the wall voltage is erased in the previous addressing. Then, by generating a discharge in all cells by use of this newly produced wall charge or the remaining wall charge, charge distribution can be made more even.
By carrying out the erase addressing, time necessary for the addressing can be shortened compared with the write addressing. More particularly, the write addressing requires about 3.7 &mgr;s per row for producing sufficient charge, while the erase addressing requires about 1.5 &mgr;s per row since the erase addressing needs only to eliminate charge.
However, when the entire screen is charged for preparation for the erase addressing, a strong discharge is generated in cells in a non-charged state by the write voltage. As a result, there is a problem in that, especially when a dark image is displayed, a background portion which occupies most of the screen is seen bright and thus contrast is reduced. When a relatively bright image is displayed, unnecessary light emission in the preparation for the addressing is not so prominent.
SUMMARY OF THE INVENTION
An object of the present invention is to reduce the brightness of the background to improve the contrast.
In the present invention, on some rows, a discharge for preparation for the erase addressing is generated not by applying voltage, but by use of space charge generated by the discharge in rows adjacent to the rows. Thereby, the total number of discharges generated in a process for producing charge on the whole screen prior to the erase addressing is reduced.
The present invention provides a method for driving an plasma display panel by use of an erase addressing to erase wall charge in a cell which need not be lighted, after charging all cells on a screen, for matrix display by an AC-driven plasma display panel constructed to generate a surface discharge across electrode pairs which extend in a direction of rows and are covered with a dielectric layer, the method comprising the steps of grouping the electrode pairs, which define rows, into a first group and a second group in such a manner that an electrode pair of one group is adjacent to at least one electrode pair of the other group, and, as an operation to charge all the cells prior to the addressing, applying, to electrode pairs belonging to either one of the first and second groups, a first voltage for generating a discharge only in cells in a non-charged state and then a second voltage for generating a discharge in all the cells, and applying the second voltage to electrode pairs belonging to the other group.
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Awad Amr
Saras Steven
Staas & Halsey , LLP
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