Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-09-04
2002-06-25
Ton, Dang (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
Reexamination Certificate
active
06411622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for detecting a timeout of a reception packet in an ATM (Asynchronous Transfer Mode) communication controller for receiving a packet formed into an ATM cell in an ATM network.
2. Description of the Prior Art
ATM (Asynchronous Transfer Mode) which is a multiplex transfer scheme for digital information in B-ISDN (broadband ISDN) allows efficient processing in accordance with the amount of information to be transferred because transfer operation need not be synchronous with the bit rate of a network. ATM is therefore widely used for high-speed, broadband communication services.
FIG. 1
shows the arrangement of an ATM network, which includes an ATM communication controller for connecting a plurality of ATM terminals
21
a
to
21
c
to a plurality of ATM servers
20
a
and
20
b
through a plurality of ATM switches
22
a
to
22
c
. Note that reference numerals
23
a
to
23
f
denote packets formed into ATM cells.
On the transmission side of each ATM communication apparatus, as shown in
FIG. 2
, a packet is segmented into ATM cells each consisting of a 5-byte header and a 48-byte payload. These ATM cells are then transmitted through a line. Each ATM cell incorporates a number called a VPI/VCI which is used to identify a virtual connection. With this number, communication of each cell between a transmission terminal and a reception terminal is realized.
In such an ATM network, a cell of this packet in a given connection may be delayed or discarded because of some kind of abnormality in the line or apparatus. In this case, all of the ATM cells may not arrive at the reception side. For this reason, a timeout of an ATM packet must be detected to terminate the processing for this connection.
As disclosed in, for example, “Users' Manual &mgr;PD98401 Local ATM SAR Chip (NEASCOT-S10)”, on the reception side of an ATM communication controller, a conventional timeout detecting section for such an ATM reception packet is used to define the time required to reassemble ATM cells into a packet, monitor in hardware whether the monitored time has exceeded the allowable time, and notify the upper layer of a timeout upon detecting it.
FIG. 3
is a block diagram showing an example of the arrangement of the ATM communication controller.
The ATM communication controller is made up of a device PHY
28
having an ATM physical layer function, an SAR (Segmentation And Reassembly) receiving section
24
for performing reception determination on the basis of the VPI/VCI value in the header of a received ATM cell, performing conversion to a VPI/VCI identification number (to be referred to as a VC hereinafter), detecting various types of errors, and reassembling ATM cells into a packet, an SAR transmitting section
25
performs ATM cell segmentation of a transmission packet and transmission cell rate control, a control memory
27
storing various pieces of information (e.g., an address for DMA and the flag of the first cell) used in the SAR receiving section
24
and the SAR transmitting section
25
, and a DMA controller
26
for performing interface control with respect to a system bus
31
to which the SAR receiving section
24
, the SAR transmitting section
25
, a CPU
29
, and system memory
30
are connected.
Upon reception of a cell, the SAR receiving section
24
checks the VPI/VCI value in the header. The payload of the reception cell for which reception is permitted is read by the DMA controller
26
and is DMA-transferred to the system memory
30
through the system bus
31
.
FIG. 4
is a block diagram showing the arrangement of a conventional ATM reception packet timeout detecting apparatus.
The ATM reception packet timeout detecting apparatus is incorporated in the SAR receiving section
24
. This apparatus includes a T
1
register
16
in which an allowable time for a timeout is set, a TS register
17
for storing the start time of “the VC through which reception was started earliest”, an adder
10
for adding the value in the T
1
register
16
to the value in the TS register
17
, a timer section
6
having a counter
7
that is incremented in synchronism with a system clock
19
supplied from the system bus
31
side, and a comparator
18
for comparing the output value from the adder
10
with the counter value of the timer section
6
.
The control memory
27
is divided into areas in units of VCs. Each VC information is stored in a corresponding area (to be referred to as a VC table hereinafter). The parameters associated with timeout detection in each of VC tables
15
a
to
15
c
include the E bit for enabling timeout detection and linking the corresponding VC to a link list, the reception start time of a packet, i.e., the arrival time (TS) of the first cell of the packet, and forward/backward pointers (EP/BP) for forming a link list.
The SAR receiving section
24
further includes a header/payload separating section
11
for separating the header and payload of a reception cell, a VPI/VCI-VC converter
12
for converting the VPI/VCI extracted from the header of the reception cell into a corresponding VC, and a reception data FIFO
13
for storing the payload of the reception cell until execution of DMA.
The operation of the conventional timeout detecting apparatus shown in
FIG. 4
will be described next.
A timeout of a reception packet is detected by a scheme of forming a link list using forward/backward pointers (FP/BP) in the corresponding VC table. In these pointers, the number of a VC through which reception was started earlier and the number of a VC through which reception was started later are respectively stored.
When a cell is received, the E bit is read out from the VC table corresponding to the reception VC. If the E bit is set and the cell is the head of a new packet, the reception VC is written in the TS area of the VC table corresponding to this VC while the counter value of the timer section
6
at this time point is regarded as the current time. If, for example, this link list has no VC, the reception VC is written in the TS register
17
at this time. After the pointers in the VC table are updated, this VC is added to the end of the link list. That is, “the VC through which reception was started earliest” is always the head of a link list, whereas “the VC through which reception was started latest” is linked to the end of the link list.
If the last cell of the packet arrives within the allowable time for a timeout which is set in the T
1
register
16
, the pointers of the corresponding VC and preceding and succeeding VCs are updated, and this VC is removed from the link list. If, for example, “the VC through which reception was started earliest” is deleted from the link list, the TS register
17
is rewritten with the reception start time of the next VC to be linked.
A timeout is therefore detected first from the VC at the head of the link list, i.e., “the VC through which reception was started earliest”. For this reason, the value obtained from the adder
10
by adding the reception start time of this VC, written in the TS register
17
, to the allowable time for a timeout set in the T
1
register
16
, is input to an input terminal A of the comparator
18
, while the counter value of the timer section
6
indicating the current time is input to an input terminal B of the comparator
18
. A timeout can be detected by comparing the two values. If the inputs to the inputs terminals A and B of the comparator
18
are equal to each other, a timeout is detected from “the VC through which reception was started earliest”.
In the conventional detecting apparatus described above, however, timeout detection cannot be performed in accordance with the cell rate or packet length in each VC. Assume that in the arrangement shown in
FIG. 4
, the periods of time required for reassembly after proper reception of packets through the respective VCs are respectively 2 msec for VCi; 4 msec for VCj; and 8 msec for VCk. In this case, the allowable time for a timeout must be
McGinn & Gibb PLLC
Ton Dang
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