Semiconductor device with constant current source circuit...

Details Semiconductor device with constant current source circuit... Semiconductor device with constant current source circuit...

2000-05-26

2002-02-19

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06348835

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with a constant current source circuit which is not influenced by noise.
2. Description of the Related Art
A conventional constant current source circuit
10
is shown in FIG.
1
. The conventional constant current source circuit
10
is composed of a constant current source section
11
and an output section
12
.
The constant current source section
11
is composed of two N-channel MOS transistors M
1
and M
2
, and two P-channel MOS transistors M
3
and M
4
. The transistor M
1
has a source directly connected to the ground (GND), and a gate and a drain connected directly to each other. The transistor M
2
is connected at its source via a resistor R
1
to the ground, at its gate to the drain of the transistor M
1
, and at its drain to the drain of the transistor M
4
. The two P-channel MOS transistors M
3
and M
4
are connected at their sources commonly to a power supply potential V
CC
and at their gates to each other. The drain of the transistor M
3
is connected directly to the drain and gate of the transistor M
1
. The drain of the transistor M
4
is connected directly to the gate of the transistor M
4
and to the drain of the transistor M
2
. The transistors M
3
and M
4
form a current mirror circuit for driving the transistors M
1
and M
2
. The transistors M
1
to M
4
form a Widlar current mirror circuit.
The output section
12
is composed of a P-channel MOS transistor M
5
. The transistor M
5
is connected at its source directly to the power supply potential V
CC
and at the gate to a node C between the drain of the transistor M
2
and the drain of the transistor M
4
in the constant current source section
11
. An output current Iout is outputted from a node F connected to the drain of the transistor M
5
.
Next, the operation principle of the constant current source circuit
10
will be described. Supposing that the current at the drain of the transistor M
3
is I
1
and the current at the drain of the transistor M
4
is I
2
in the current mirror circuit of the transistors M
3
and M
4
, a ratio between the transistor M
3
ratio and the transistor M
4
ratio is expressed as I
1
:I
2
. The ratio indicates a ratio of the gate widths or the sizes of the transistors. For simplifying the description of the operation principle, it is supposed that the M
3
ratio is equal to the M
4
ratio, i.e., the transistors M
3
and M
4
are identical in capability ratio and the M
2
ratio is equal to 10 times of the M
1
ratio.
FIG. 2
is a graph showing sub-threshold characteristics of the transistors M
1
and M
2
. As seen from
FIG. 2
, when the same gate—source voltage V
GS
is applied to the transistors M
1
and M
2
, the transistor M
2
flows a current 10 times greater than that of the transistor M
1
.
As shown in
FIG. 2
, the voltage V
1
at the current I
1
of the transistor M
1
is equal to the gate—source voltage V
GS
of the transistor M
1
. More particularly, the voltage V
1
is a voltage at a node B shown in FIG.
1
. The voltage V
2
at the current
12
of the transistor M
2
is equal to the voltage V
GS
of the transistor M
2
. More specifically, (voltage V
2
)=(voltage at node B)−(voltage at a node D). If the voltage difference (V
1
−V
2
) is equal to &Dgr;V, the voltage difference &Dgr;V is an electromotive force due to the resistor R
1
, and I
2
=&Dgr;V/R
1
is satisfied. The voltage difference &Dgr;V is equal to a sub-threshold coefficient. The sub-threshold coefficient is defined as the voltage difference &Dgr;V
GS
necessary to change the current for one digit.
The output current lout is determined as (&Dgr;V/R
1
)×(M
5
ratio/M
4
ratio). Thus, the current outputted from the constant current circuit becomes a constant current.
It should be noted that the M
3
ratio is equal to the M
4
ratio for simple description in the above. However, the ratios of the transistors are not limited to them. The output current lout is determined depending on the ratios of the transistors M
1
to M
5
and the resistance of the resistor R
1
.
The conventional constant current source circuit
10
described above may be used, for example, in a reference voltage generating circuit shown in FIG.
3
. In the reference voltage generating circuit
20
, a node F in the constant current source circuit
10
is connected to the ground via a resistor r and a diode D
1
. An output voltage Vout is outputted from the node F.
As shown in
FIG. 2
, as the temperature is increased, the inclination of the sub-threshold curves becomes small due to the transistor characteristics. As a result, the sub-threshold coefficient increases. Hence, as the temperature is increased, the voltage difference &Dgr;V is also increased. This results in the increase of the output current lout from the constant current source circuit
10
so that the electromotive force of the resistor r, i.e., (Vout)−(voltage at node G) is increased. Meanwhile, as the temperature is increased, the built-in potential of the diode D
1
becomes low. This results in the decrease of the voltage at the node G in a higher temperature. Thus, the output current Iout is controlled using the ratios of the transistors M
1
to M
5
and the resistance of the resistors R
1
and r so that the influence due to the temperature characteristic can be cancelled. Therefore, the output reference voltage Vout can be obtained free from variations in the temperature. Also, when the resistors R
1
and r are formed of the same material at the same time, changes in their resistances caused by the temperature change or the production deviation can be cancelled as shown in FIG.
4
.
In a DRAM employing an N-channel transistor as a memory cell transistor, the substrate potential (V
BB
) of the memory cell transistor is needed to be set to a negative value for the improvement of the hold characteristic of the memory cell.
The well structures in the DRAM are classified into two types, a twin well and a triple well. In the twin well type, the substrate potential of an N-channel transistor in a peripheral circuit (a logic section) on a P-type substrate is set to V
BB
, because the substrate potential is common to that of a memory cell section. On the contrary, in the triple well type, the substrate potential of an N-channel transistor in the peripheral circuit is electrically isolated from the substrate potential of the memory cell section. Therefore, both of the substrate potentials can be determined individually and independently. While the substrate potential of the memory cell section is the potential V
BB
, the substrate potential of the peripheral circuit is the GND potential.
The constant current source circuit
10
shown in
FIG. 1
is formed in a peripheral circuit. In the triple well type, the substrate potential of the N-channel transistor in the peripheral circuit is the GND potential and not affected by the V
BB
noise. That is, the V
BB
noise has no influence in the constant current source circuit
10
shown in FIG.
1
. On the other hand, in a twin well type, it is necessary to remove the V
BB
noise. Adoption of the twin well type reduces the manufacturing cost, compared with the triple well type.
FIG. 5
is a cross sectional view showing an example of N-channel MOS transistors. The N-channel transistor
31
is formed in a P-type substrate
34
. A junction capacitance Cj is formed between an N-type diffusion layer
35
of the N-channel transistor
31
and the P substrate
34
. The junction capacitance Cj is about 0.5 fF (femto-farads, 1×10
−15
F) per square micrometer of the N diffusion layer
35
. As shown in
FIG. 5
, the P-type substrate
34
is connected to a node with the V
BB
substrate potential via a sub-contacts Sc.
FIG. 6
illustrates an inverter
40
which is composed of a P-channel transistor
41
and an N-channel transistor
32
. Here, it is supposed that the N-channel transistor
32
in the inverter
40
is shown in FIG.
5
. When the inverter
40
operates, the potential at

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