Reverse level shift circuit and power semiconductor device

Details Reverse level shift circuit and power semiconductor device Reverse level shift circuit and power semiconductor device

2002-04-09

2002-12-24

Vu, Bao Q. (Department: 2838)

Electric power conversion systems

Current conversion

Constant current to constant voltage or vice versa

C363S074000

Reexamination Certificate

active

06498738

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reverse level shift circuit for converting a voltage signal on high-voltage side to a voltage signal on low-voltage side, which is used in a power semiconductor device.
2. Description of the Background Art
In a HVIC (high voltage integrated circuit) on which, for example, an inverter, its driving circuit and its protection circuit are contained in a single chip, there is generally a detector for detecting voltage signals. This detector detects whether an abnormal voltage upsurge occurs in the respective switching elements on high-voltage side and low-voltage side of the half bridge of each phase.
FIG. 6
is a diagram illustrating an exemplary configuration of a power semiconductor device containing a circuit to detect whether an abnormal voltage upsurge occurs in a switching element on high-voltage side of a single-phase half bridge. On this circuit, for example, switching elements SW
1
and SW
2
such as IGBT (insulated gate bipolar transistor) are connected in series, and free wheel diodes D
1
and D
2
are subjected to inverse-parallel connection with the switching elements SW
1
and SW
2
, respectively. These parts form a half bridge for one phase. The switching element SW
1
on high-voltage side serves as a multi-emitter, to one output terminal of which one terminal of a shunt resistance SH is connected. By monitoring the value of voltage drop in the shunt resistance SH, it is detectable whether an abnormal voltage upsurge occurs in the switching element SW
1
. The other terminal of the shunt resistance SH is connected to a connection point MP of the switching elements SW
1
and SW
2
.
An output signal of voltage drop in the shunt resistance SH is, for example, converted to a digital signal through an AD (from analog to digital) conversion circuit AD, and then inputted to a reverse level shift circuit IS. Hereat, the reverse level shift circuit IS functions to transfer a signal change of voltage drop (i.e., VIN-HGND) in the shunt resistance SH, while lowering its reference potential from potential HGND in the connection point MP to grounded potential GND that is a reference potential of other circuit.
The potential HGND at the connection point MP is high and in a float condition. For detecting output signals, it is therefore desirable that the reference potential is lowered to the grounded potential GND. Especially in the case of polyphase circuits such as three-phase circuit, one micro-processor in a HVIC detects an output signal of each phase and judges whether it is abnormal or not (e.g., it is judged abnormal when voltage upsurges in the shunt resistance exist in two phases). Hence, all the reference potentials of output signals should be lowered to the grounded potential GND, and it is for this reason that the reverse level shift circuit IS is present.
An output signal of the reverse level shift circuit IS (VOUT-GND) is inputted to an abnormality detection/stop signal output circuit DT equivalent to the above-mentioned microprocessor. On this circuit DT, it is detected whether there is an abnormal voltage drop at the shunt resistance SH in each phase, and if an abnormality is detected, a stop signal Sc for stopping the operation of the switching element SW
1
is outputted.
The stop signal Sc is applied to a control electrode of the switching element SW
1
via a level shift circuit LS and an output circuit OU. The level shift circuit LS functions to transfer the stop signal Sc while increasing its reference potential from the grounded potential GND to the potential HGND of the connection point MP. The output circuit OU functions to amplify the output of the level shift circuit LS.
In the forgoing description, it is not essential that an output signal of voltage drop at the shunt resistance SH be converted to a digital signal by the AD conversion circuit AD. For instance, if the reverse level shift circuit IS or abnormality detection/stop signal output circuit DT can process signals of analog input, the AD conversion circuit AD may be omitted so as to directly input a signal change of voltage drop to the reverse level shift circuit IS.
FIG. 7
is a diagram illustrating a conventional configuration of a reverse level shift circuit IS. On a reverse level shift circuit IS
4
, a high-side signal detecting circuit HD comprising a comparator etc. receives an input signal VIN and judges whether the value of voltage drop at a shunt resistance SH is greater than a predetermined value. When the former is larger than the latter, the high-side signal detecting circuit HD activates output.
The output of the high-side signal detecting circuit HD is applied via an inverter IV
6
to the gate electrode of a Pch-DMOS (P-channel double diffusion metal oxide semiconductor) transistor PD
1
. When the output of the high-side signal detecting circuit HD is activated, the Pch-DMOS transistor PD
1
enters operating state to flow current between its source and drain. Each circuit on the high-side is driven by a higher potential HVCC that a power source V
1
generates from the potential HGND.
Since the Pch-DMOS transistor PD
1
has high breakdown voltage and breakdown voltage characteristic of several hundreds volt level, it functions as a high-breakdown voltage resistance to perform reverse level shift of signals between the potential HVCC that is high and the grounded potential GND that is low. Current passing through the Pch-DMOS transistor PD
1
flows to a resistance R
5
on the low side, at which the current is converted to a voltage signal. A voltage drop at the resistance R
5
is transferred to an inverter IV
7
and an output circuit OT comprising an amplifier etc., and then outputted as an output signal VOUT. Each circuit on the low side is driven by a higher potential VCC that a power source V
2
generates from the grounded potential GND.
Thus, the Pch-DMOS transistor PD
1
is employed on the reverse level shift circuit IS
4
. From the viewpoint of voltage control between source and gate, in general, a Pch-transistor is employed on a reverse level shift circuit and a Nch-transistor is employed on a level shift circuit. Accordingly, when a level shift circuit and a reverse level shift circuit are allowed to coexist, it is necessary to form Nch- and Pch-DMOS transistors in a HVIC.
In manufacturing the DMOS transistors, however, it is difficult to form both of the Nch- and Pch-DMOS transistors in the HVIC, while adjusting characteristics, such as the threshold values of both transistors, to their respective desired values. It is especially difficult to form a Pch-DMOS transistor in a substrate at which a Nch-DMOS transistor is present. Hence, it is desired to configure a reverse level shift circuit without employing any Pch-DMOS transistor.
It can also be considered to configure a reverse level shift circuit using photocouplers, without using any DMOS transistor. However, the use of photocouplers increases the number of parts, which tends to raise the cost and results in poor reliability at high temperatures. From the standpoint of the entire arrangement, the configuration preferably contains a transistor that operates electrically.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a reverse level shift circuit that converts an input voltage signal using a first potential as a reference potential to an output voltage signal using a second potential lower than the first potential, as a reference potential, and then outputs the output voltage signal, comprises: a voltage-current conversion part operating based on the first potential, which converts the input voltage signal to a current signal corresponding to a value of the input voltage signal, then outputs the current signal; a Nch-MOS transistor having a source to which the second potential is applied via a load, a drain responsive to the current signal from the voltage-current conversion part, and a gate to which a fixed potential is applied; and a current-voltage conversion part operating based on the second potential, which co

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