Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2001-06-29
2002-08-27
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S016000, C438S401000
Reexamination Certificate
active
06440759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for concurrently measuring Critical Dimension (CD) and overlay structures on a semiconductor chip by combining the structures into a single feature to enable measurements to be made in a single pass in the CD scanning electron microscope (SEM).
2. Description of the Prior Art
In producing semiconductor devices that are of Large Scale Integration (LSI) and Very Large Scale Integration (VLSI), extremely complex electrical circuits are fabricated on a chip of silicon. This fabrication has occasioned substantial reductions in the size of circuit dimensions and thereby altered the manufacturing requirements of the semiconductor devices.
In the manufacturing process, photolithography is typically utilized to transfer a microscopic pattern from a photomask to the silicon wafer surface of an integrated circuit. The typical photolithographic system employs a step-and-repeat process that transfers the mask pattern from a macroscopic prototype to the silicon wafer. The process entails numerous iterations of individual reductions, and each individual reduction may introduce errors into the final device. Conventional means for monitoring and correcting these errors fail to provide the necessary resolution and measurement accuracy when employed with extremely small chip designs necessitated by the required reductions.
By increasing the number of components in semiconductor structures, integrated circuit configurations have developed into complex three dimensional topographies.
As the device dimensions continue to be reduced, the requirement for overlay measurement accuracy continues to increase. In general, for a 0.25 &mgr;m design rule, the overlay specification is in the range of about 0.025 &mgr;m. Consequently, overlay measurements have to utilize SEM (scanning electron microscopy) techniques to verify measurement accuracy).
One conventional wafer product overlay measurement technique employs test mask targets (i.e., box-in-box and critical dimension (CD) in different areas of the wafer, where these structures are layed out in the peripheral regions of the chip. These measurements compare shifts in the box centerlines in order to obtain a process average. However, with this conventional technique, the disposition of the dimensional quality or diagnostics is not capable of being determined until both the box-in-box and critical dimension targets are taken on a significant number of cells within the device. In other words, since this process requires two sets of measurement steps, and a comparison between the measurements, the method is unwieldly. Further, this conventional diagnostic process is more exaggerated with increased density of devices and thereby impedes the automated fabrication process.
U.S. Pat. No. 5,555,319 disclose critical dimension measuring methods and equipment therefor. The measuring equipment comprises:
irradiating means for irradiating an electron beam onto a measured pattern to be measured;
detecting means for detecting a secondary and reflected electron reflected from the measured pattern;
filtering means for receiving image data as the secondary and reflected electron detected by the detecting means and implementing a spatial filtering processing of the image data and storing the result of the spatial filtering processing into a first memory;
histogram processing means for receiving the image data which had been obtained after the spatial filtering processing stored in the first memory, implementing histogram processing of the image data, and storing the result of the histogram processing into a second memory;
threshold value detection means for receiving the result of the histogram processing stored in the second memory, generating a threshold value by automatically separating classes in a histogram obtained by the histogram processing based on the discriminant criteria method, and storing the result generated by the threshold value detection means into a third memory;
three-value conversion processing means for receiving the threshold value stored in the third memory, implementing three-value conversion of the image data stored in the first memory obtained after special filtering processing based on the threshold value, and storing the result obtained by the three-value conversion means into a fourth memory.
first calculation means for receiving image data stored in the forth memory obtained after three-value conversion processing, obtaining the area and perimeter of the bottom section of the pattern based on this data, and storing the result obtained by the first calculation means into a fifth memory;
second calculation means for receiving the area and the perimeter of the bottom section of the pattern stored in the fifth memory, obtaining the diameters of the pat-terms based on this data, and storing the result obtained by the second calculation means into a sixth memory; and
pattern shape recognition means for automatically deciding whether the pattern is circular or elliptical based on the pattern diameter stored in the sixth memory, calculating the diameter of the circle based on the area if the pattern is circular, and calculating a major axis and a minor axis of the ellipse based on the area and the perimeter if the pattern is elliptical.
A CD vernier apparatus for SEM CD measurements is disclosed in U.S. Pat. No. 5,847,818. The apparatus comprises:
a central strip pattern disposed along a specific direction;
a first plurality of strip patterns disposed in parallel, along the specific direction, and on a first side adjacent to the central strip;
a second plurality of strip patterns disposed in parallel, along the specific direction, and on a second side adjacent to the central strip pattern;
a plurality of recognition patterns selectively added to the first plurality of strip patterns and to the second plurality of strip patterns;
wherein the number of strip patterns of the first plurality equals that of the number of strip patterns of the second plurality, each strip pattern having an equal length which is shorter than the length of the central strip pattern but is longer than the length of the recognition patterns, and wherein one end of the central strip pattern, one end of each strip pattern of the first plurality and one end of each strip pattern of the second plurality all being aligned on a base line, whereby the central strip pattern, the recognition patterns, the first plurality and the second plurality form a specific figure to serve as a critical dimension vernier pattern.
A method of apparatus for obtaining two or three dimensional information from scanning electron microscopy is disclosed in U.S. Pat. No. 6,054,710. The method comprises:
collecting a first measurement of a first semiconductor structure from a scanning electron microscope;
collecting a second measurement of the first semiconductor structure from an atomic force microscope;
establishing a relationship between the first measurement and the second measurement of the first semiconductor structure wherein the relationship indicates the second measurement if a third measurement from a scanning electron microscope of a second semiconductor structure has characteristics similar to the first semiconductor structure; and
mapping a two dimensional waveform through a multi-dimensional decision space to a corresponding three dimensional characteristic using a parallel distributed process operationally connected to an output of the scanning electron microscope, the parallel distributed process containing coefficients that provide the multidimensional mapping space for the output of the scanning electron microscope to map to an output value that provides information on the critical dimension of the semiconductor structure.
U.S. Pat. No. 5,701,013 disclose a wafer metroloty pattern for use in a critical dimension analysis of a semiconductor configuration comprising:
a first central section for providing a central reference point;
a plurality of sections positioned concentrically around the central s
Commons Martin
Klee Velt
Mono Tobias
Pohl John
Wensley Paul
Braden Stanton
Chaudhari Chandra
Infineon - Technologies AG
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