Clock noise reduction apparatus

Details Clock noise reduction apparatus Clock noise reduction apparatus

2001-05-02

2002-10-08

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S386000, C327S387000

Reexamination Certificate

active

06462604

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to electronic circuitry. More specifically, the invention relates a method for reducing the noise associated with a clock signal for a flip-flop based circuit.
2. Background Art
In all microprocessor-based systems, including computers, the clock circuit is a critical component. The clock circuit generates a clock signal that is a steady stream of timing pulses that synchronize and control the timing of every operation of the system.
FIG. 1
shows a prior art diagram of an ideal clock signal
10
. An entire clock cycle
12
includes a rising or leading edge
14
and a falling or trailing edge
16
. These edges
14
,
16
define the transition between the low and high value of the signal.
FIG. 2
shows a block diagram of a prior art local clock signal distribution system. The clock signal
30
a
is input to a clock header
32
which serves to buffer the clock signal. From the header
32
, the clock signal
30
b
is input to an edge-triggered flip flop
34
(“flip-flop”) where it serves to trigger the flip-flop. A flip-flop is a memory device that is commonly used in integrated circuits. It is dependent upon a clock signal to initiate its function. Flip-flops generally take input data and distribute output data on the rising edge of a clock signal. However, a flip-flop could be configured to work on the falling edge of a clock signal.
FIG. 3
shows a digital logic schematic of the prior art local clock signal distribution system as shown in FIG.
2
. The clock signal
30
a
is input to the clock header
32
. The clock header
32
includes a NAND gate
36
and an inverter
38
a
. Once inside the clock header
32
, the clock signal
30
a
is one of the inputs to the NAND gate
36
. The other NAND input
42
is a signal that is HIGH so that the gate
36
simply inverts the value of the clock signal
30
a
. The NAND input
42
is switched to LOW to turn off the clock header
32
if needed. Next, the signal
30
a
passes through the inverter
38
a
which inverts the signal back to its original value. The clock signal
30
b
then passes from the clock header
32
to the flip-flop
34
. Once in the flip-flop
34
, the signal
30
b
is split into two paths. The first path passes through one inverter
38
b
, and the second path passes through two consecutive inverters
38
c
and
38
d
. Each path feeds into the internal circuitry of the flip-flop
40
along with the DATA_IN
44
and DATA_OUT
46
paths of the flip-flop
34
.
Clock noise problems on the system power grid are usually caused by the large amount of current that is used in clock signal distribution. This current comes from the switching transistors that control the clock signal. As these transistors switch states, the current noise spikes onto the power grid due to the current demand or “current draw” of the switching transistors. These high current demands cause noise in the system voltage supply due to voltage (IR) drops and inherent system inductance (L di/dt). A clock signal distribution circuit uses a significant amount of current in a short amount of time because the spikes occur twice per clock cycle: once on the current draw of the leading edge and once on the current draw of the falling edge of the signal. This puts the noise at a very high frequency (2× the clock frequency). This noise can cause missed timing if the clock signal voltage is too low or component failure if the clock signal voltage is too high. The noise can even escape “off the chip” and affect the other components of the system.
FIG. 4
shows a graph of current draw during a clock cycle period of the prior art embodiment shown in FIG.
3
. The flip-flop of this embodiment is triggered on the rising edge of a clock signal. The value “I”
35
represents the full value of a current draw. The value “¾ I”
37
represents 75% of the full value while the value “½ I”
39
represents 50% of the full value. The first current draw
41
of the graph represents the draw that results from the leading edge of a clock cycle (at clock cycle=0). The second current draw
43
represents the draw that results from the falling edge of the clock cycle (at clock cycle=t/2). As shown, the leading edge draw
41
is the full value of current draw. The trailing edge draw
43
is about half the value of the leading edge draw
41
. In this example, the first draw
41
is larger than the second draw
43
because all of the flip-flop's change on the rising edge of the clock signal. Since none of the flip-flops change on the falling edge, the second draw
43
is smaller.
A common technique to alleviate noise is adding additional power to the grid. This power is added upon sensing a voltage drop due to noise. However, such techniques only respond to noise at a much lower frequency than clock noise and also respond only to a certain threshold of noise. Consequently, a need exists for a technique that generates a response to clock noise at a synchronized frequency with the clock noise itself.
SUMMARY OF INVENTION
In some aspects, the invention relates to an apparatus for reducing noise of a clock signal for a flip-flop based circuit, comprising: a charge control circuit that initiates storing a charge upon receipt of a first pre-determined signal; and a dump control circuit that initiates dumping the charge onto a system power grid upon receipt of a second predetermined signal.
In another aspect, the invention relates to an apparatus for reducing the noise of a clock signal for a flip-flop based circuit, comprising: means for initiating a charge control circuit that stores a charge upon receipt of a first predetermined signal; and means for initiating a dump control circuit that dumps the charge onto a system power grid upon receipt of a second pre-determined signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 4370620 (1983-01-01), Tin
patent: 4672325 (1987-06-01), Murai
patent: 5164611 (1992-11-01), Summe
patent: 5311077 (1994-05-01), Brown
patent: 5539337 (1996-07-01), Taylor et al.
patent: 5754068 (1998-05-01), Kumagai

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