Data retention registers

Details Data retention registers Data retention registers

2001-02-13

2002-08-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000

Reexamination Certificate

active

06437623

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data retention registers in a data processing system, and more particularly, to a data retention latch for preserving data in a power-down mode of the system.
2. Description of the Related Art
In electronic systems, power consumption is one of the factors determining efficiency and functionality of the system. Especially, with the proliferation of wireless and portable electronic devices such as palm top computers, cellular telephones, etc., power consumption has become an important factor to be considered in designing and manufacturing such electronic devices. This is because such electronic devices are typically subject to the limitation of battery lifetime, a duration of usage of a battery or a duration of usage between charges in case of a rechargeable battery. Thus, in battery-operated portable electronic devices as well as other power-saving electronic devices, much effort has been devoted to reduce the power consumption of the devices.
In modern electronic systems, power-saving techniques have been introduced to reduce the power consumption. One power-saving technique is employing a “sleep mode” (or power-down mode) . In this technique, while an electronic system is not in active use, the system is rendered into the sleep mode to save the power dissipated in the system. In the sleep mode, no power is theoretically supplied to electronic circuits in the system, except for circuits to which the power is inevitably necessary for a proper operation to bring the device to an active mode following the sleep mode. In other words, the main power for the system may be turned off in the sleep mode, and only selective power lines are maintained for the minimum number of circuits for the proper operation.
The system returns to an active mode from the sleep mode when a user resumes an active use on the system. The transitional state of the system from the sleep mode to the active mode is called a “wake-up” mode.
In order for an electronic system to recover from the sleep mode to the wake-up mode and then to the active mode, some necessary data should remain during the sleep mode in a data storage section of the system. Data retention registers are typically used to preserve such necessary data while the system is in the sleep mode. In the absence of such a process and/or registers for preserving data necessary for returning to the active mode, it will be necessary to reenter the data when the system is recovered to the active mode from the sleep mode.
In the sleep mode, although no switching activity occurs and the selective power lines are maintained to preserve the necessary data, the data retention registers may still lose the data preserved therein due to the leakage current in the circuits of the registers.
To reduce such a risk of losing the data preserved in the data retention registers, high-threshold voltage transistors are employed in the circuits of the registers. This is because the leakage current in the high-threshold voltage transistors is much smaller than that in transistors with the normal threshold voltage, although the high-threshold voltage transistors are not able to provide the same speed as the normal threshold voltage transistors from a reduced overdrive voltage.
Referring to
FIG. 1
, there is provided a circuit diagram of a conventional data retention system
10
. The data retention system
10
has master-slave latches
12
,
14
which are commonly used for storing data. The master-slave latches
12
,
14
hold data provided through an input terminal IN, and output the held data through an output terminal OUT. The data retention system
10
also has a “balloon” circuit
16
connected to the master-salve latches
12
,
14
. The balloon circuit
16
preserves the data which are held in the master-slave latches
12
,
14
in a sleep mode (i.e., power-down mode). The balloon circuit
16
has input and output terminals Si, SO for receiving and generating data, respectively. When the data retention system
10
(or an entire data processing system including the data retention system
10
) is rendered into the sleep mode, a power supply (not shown) for the system including the master-slave latches
12
,
14
is turned off so that the master-slave latches
12
,
14
receive substantially no power, i.e., substantially zero (0) supply voltage. On the other hand, the balloon circuit
16
continuously receives a predetermined supply voltage in the sleep mode as well as the active mode from an independent power supply (not shown). As a result, the balloon circuit
16
can preserve the data read from the master-slave latches
12
,
14
during the sleep mode.
As shown in
FIG. 1
, the balloon circuit
16
is completely paralleled with the master-slave latches
12
,
14
. In other words, the balloon circuit
16
has substantially identical elements and configuration as those of the master-slave latches
12
,
14
. Only difference between the balloon circuit
16
and the master-slave latches
12
,
14
is that the balloon circuit
16
employs high-threshold voltage transistors. This is because by using the high-threshold voltage transistors data preserved in the balloon circuit
16
can be prevented from being lost due to a leakage current.
The balloon circuit
16
, for example, includes a pass gate transistor TG which separates the balloon circuit
16
from the master-slave latches
12
,
14
. Since the pass gate transistor TG has a high-threshold voltage, the leakage current in the balloon circuit
16
is cut off by turning off the pass gate transistor TG.
In the sleep mode, under the control of sleep mode clock signals SL
1
, SL
2
, the balloon circuit
16
remains active to preserve the data read from the master-slave latches
12
,
14
, and the pass gate transistor TG is turned off to prevent the leakage current, while the master-slave latches
12
,
14
are inactive. When the system
10
is recovered to the active mode, the master-slave latches
12
,
14
become active and the data preserved in the balloon circuit
16
is loaded into the master-slave latches
12
,
14
. Examples of data retention registers are disclosed, for example, in “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits”, by S. Shigematsu et al., June 1997, IEEE Journal of Solid-State Circuits, Vol. 32, No. 61 , pp. 861-869, whose disclosures are herein incorporated by reference.
However, since a conventional data retention circuit (e.g., the balloon circuit) is completely paralleled with corresponding master-slave latches as described above, the data retention circuit should have the substantially identical number of transistors as those in the master-slave latches. Such a structure amounts to a hindrance factor in improving the integration density of the circuits.
In addition, the conventional data retention circuit employs the high-threshold voltage transistors to prevent the preserved data from being lost due to the leakage current. As well known to those skilled in this art, high-threshold voltage transistors may cause the data processing system degraded, such as causing a decrease in data read/write speed in a data storage device.
Further, it is necessary to provide an independent power supply for the data retention circuit to preserve data in the sleep mode. The independent power supply should continuously provide a supply voltage to the data retention circuit independent of the status of a main power supply for the system.
Therefore, a need exists for a data retention circuit for preserving data in a sleep mode without degrading the performance of the system. It is desired that a data retention circuit has a simpler design so as to improve the integration density of the circuits. It would be also advantageous to provide a data retention circuit for preserving data in a sleep mode without requiring a supply voltage from an independent power supply.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data retention system for preserving data in a

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