Integrated circuitry

Details Integrated circuitry Integrated circuitry

1999-10-20

2002-02-26

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S755000

Reexamination Certificate

active

06351038

ABSTRACT:

TECHNICAL FIELD
This invention relates to an integrated circuit and semiconductor processing methods of making electrical connection between an electrically conductive line and a node location.
BACKGROUND OF THE INVENTION
Single semiconductor devices are grouped into integrated circuits, which in turn are further densified into large scale integrated semiconductor systems. The trend in semiconductor integrated circuitry fabrication continues to involve a decrease in the size of individual structures. However, this has been accompanied by an increase in the complexity and number of such structures aggregated on a single semiconductor integrated chip.
One type of integrated circuitry comprises memory circuitry. This invention arose out of problems or challenges inherent in producing a particular type of memory circuitry, namely static random access memory (SRAMs). Such circuitry typically interconnects a gate of one transistor device to a diffusion area of another transistor device in a semiconductor substrate. One typical prior art method of accomplishing such fabrication and interconnection is described with reference to
FIGS. 1-4
.
FIG. 1
illustrates a semiconductor wafer fragment
10
comprised of a bulk substrate region
12
and field oxide regions
13
. A gate oxide layer
14
overlies silicon substrate
12
. A polysilicon layer
15
is provided over field oxide regions
13
and gate oxide layer
14
. Such will be utilized for fabrication of a transistor gate line of associated SRAM circuitry. A layer
16
of photoresist is provided atop the substrate, and provided with an opening
17
therein.
Referring to
FIG. 2
, a contact opening
18
to bulk substrate
12
has been etched through polysilicon layer
15
and gate oxide layer
14
. A desired diffusion region
20
is provided as shown. Then, the photoresist layer
16
of
FIG. 1
is stripped.
Referring to
FIG. 3
, a subsequent polysilicon layer
22
is deposited over first polysilicon layer
15
and to within contact opening
18
.
Referring to
FIG. 4
, layers
22
and
15
are patterned and etched to produce the illustrated transistor gate line
24
which extends over and ohmically connects with diffusion region
20
.
It would be desirable to improve upon such a construction and method for producing such a construction. The artisan will also appreciate applicability of the invention to fabrication of constructions other than SRAM circuitry.


REFERENCES:
patent: 5138425 (1992-08-01), Ichikawa
patent: 5168076 (1992-12-01), Godinho et al.
patent: 5349229 (1994-09-01), Wei et al.
patent: 5352923 (1994-10-01), Boyd et al.
patent: 5393689 (1995-02-01), Pfiester et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5432129 (1995-07-01), Hodges
patent: 5439848 (1995-08-01), Hsu et al.
patent: 5475240 (1995-12-01), Sakamoto
patent: 5497022 (1996-03-01), Sakamoto
patent: 5502324 (1996-03-01), Hachisuka et al.
patent: 5541455 (1996-07-01), Hodges
patent: 5672901 (1997-09-01), Abernathey et al.
patent: 5681778 (1997-10-01), Manning
patent: 5686736 (1997-11-01), Natsume
patent: 5798295 (1998-08-01), Hoover et al.
patent: 5877046 (1999-03-01), Yu et al.
Wolf, Stanley, Ph.D., “Silicon Processing for the VLSI Era”, vol. 1., pp. 181-182, 264-267.

Affiliated with

Also associated with

Rating

Integrated circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuitry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2956729