Method of erasing data stored in a nonvolatile memory

Details Method of erasing data stored in a nonvolatile memory Method of erasing data stored in a nonvolatile memory

2001-06-13

2002-10-08

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

06462991

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory. In particular, the invention relates to a method of erasing data stored in a nonvolatile memory.
2. Description of the Related Art
A nonvolatile memory can be used as an analog memory, or a multi-value memory. A conventional memory cell of a nonvolatile memory comprises a transistor, which has a floating gate and control gate. The memory cell holds data as a threshold voltage Vt of the transistor. Each memory cell can have a plurality of threshold voltages Vt, and the threshold voltage Vt of each memory cell corresponds to data. If electrons are introduced into the floating gate, the threshold voltage becomes greater. On the other hand, if electrons are pulled out from the floating gate, the threshold voltage becomes smaller. The threshold voltage Vt depends on the amount of electrons present in the floating gate. In this specification, “erase” means pulling out electrons, and “write” means introducing electrons in order to simplify the description hereinafter.
When the data stored in a nonvolatile memory is erased, data is written into all of the memory cells before erasing. That is to say, the threshold voltages Vt of some of the memory cells are made greater. The reason is to avoid the threshold voltage Vt from becoming less than 0 v after erasing.
An analog memory or a multi value memory has a variety of threshold voltages. The variation of the threshold voltage is between V
0
L~V
0
H (V
0
L<V
0
H) or V
1
L~V
1
H (V
1
L<V
1
H). V
0
L~V
0
H corresponds to a state that the memory cell does not contain data, and V
1
L~V
1
H corresponds to a state that the memory cell contains data. All of the memory cells of these memories have data written thereinto before erasing, in order that the threshold voltages Vt of the memory cells stabilize after erasing. The highest threshold voltage (V
1
H) of the plurality of threshold voltages may be applied to write data into the memories before erasing. However, if the difference voltage &Dgr;V of the highest threshold voltage (V
1
H) and the threshold voltage after erasing (for example 0 v) is too great, a high voltage &Dgr;V has to be erased. This may result in unevenness of the threshold voltages Vt after erasing.
On the other hand, it is not preferable that a lower voltage Vt (for example lower than V
1
L) is applied to write data before erasing in order to decrease the difference voltage &Dgr;V. This is because the memory cells, which may have higher threshold voltages Vt such as V
1
H, may remain as having higher threshold voltages V
1
H, because the lower voltage V
1
L results in a difference voltage &Dgr;V, that is not enough to erase the higher threshold voltages in this case.
As described above, there are cases that the threshold voltages Vt after erasing are not in a range of a margin of error (V
0
L~V
0
H). This may result in a wrong data being stored in the nonvolatile memory.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a method of erasing data stored in a nonvolatile memory which substantially overcomes one or more of the problems due to the limitations and the advantages of the related art.
To solve the above problems, a method for erasing data of nonvolatile memory includes adjusting a threshold voltage of a memory cell transistor to a first threshold voltage; adjusting the threshold voltage of the memory cell transistor to a second threshold voltage, the second threshold voltage being lower than the first threshold voltage; adjusting the threshold voltage of the memory cell transistor to a third threshold voltage, the third threshold voltage being higher than the second threshold voltage and being lower than the first threshold voltage and adjusting the threshold voltage of the memory cell transistor to a fourth threshold voltage, the fourth threshold voltage being lower than the second threshold voltage.


REFERENCES:
patent: 5946231 (1999-08-01), Endoh et al.
patent: 6091637 (2000-07-01), Hakozaki
patent: 10-083685 (1998-03-01), None
patent: 11-176171 (1999-07-01), None
patent: 11-176175 (1999-07-01), None

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