Block interleave circuit

Details Block interleave circuit Block interleave circuit

1999-12-21

2002-11-05

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S101000

Reexamination Certificate

active

06476738

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a block interleave circuit for segmenting a constant amount of data in input data into one block and converting a time-sequential order of the data in the block.
2. Description of the Related Art
In a digital communication system, in order to correct data error caused between a transmitting apparatus and a receiving apparatus, the transmitting apparatus is provided with a circuit for carrying out error correction coding of a transmitted signal and the receiving apparatus is provided with a circuit for decoding a signal which has been subjected to the error correction coding.
Further, the circuit for carrying out error correction coding of the transmitting apparatus is further provided with a block interleave circuit for segmenting n×d pieces of data into one block and converting a time-sequential order of the data in the block for thinning bit errors generated in a burst on a transmission path with a purpose of promoting error correction function. Further, the receiving apparatus for receiving an interleaved signal is provided with a deinterleave circuit for recovering a transmitted signal from the transmitting apparatus in an original time-sequential order.
In respect of an method of carrying out time-sequential conversion of data in a block interleave circuit, there has conventionally been known a system of using a plurality of pieces of storages as described in, for example, Japanese Unexamined Patent Publication No. 6-216882 and Japanese Unexamined Patent Publication No. 4-168811.
FIG. 5
shows an example of a circuit constitution of such a conventional block interleave circuit. An explanation will be given of a method of time-sequentially converting data in the conventional block interleave circuit in reference to FIG.
5
.
The conventional block interleave circuit is constituted by a write address forming circuit
14
, a read address forming circuit
15
, a write/read address switching circuit
16
, RAMs (Random Access Memory)
17
and
18
and a data write/read switching circuit
19
.
Input data Din is inputted from a data input terminal
11
and a frame signal Fin is inputted from a frame signal input terminal
12
to the data write/read switching circuit
19
in synchronism with an input clock Cin inputted from a clock input terminal
13
. Here, the frame signal Fin is a signal for indicating break of a block of the input data Din.
The data write/read switching circuit
19
generates a write/read switching signal
201
having a unit of n×d pieces of a block and provides the signal to the write address forming circuit
14
. The write address forming circuit
14
forms a write address signal to RAM
17
and RAM
18
with the write/read switching signal
201
as a reference. Further, the read address forming circuit
15
is synchronized with the write address forming circuit
14
and generates a read address signal to RAM
17
and RAM
18
.
The write/read address switching circuit
16
controls to switch to alternately provide the write address signal from the write address forming circuit
14
and the read address signal from the read address forming circuit
15
to RAM
17
and RAM
18
by using the write/read switching signal
201
. At the same time, the data write/read switching circuit
19
controls RAM
17
and RAM
18
to carry out read/write operation of data alternately.
FIG.
6
A and
FIG. 6B
show an outline of operational directions of read/write of RAM
17
and RAM
18
. Now, assume that operation of data write is carried out to RAM
17
and operation of data read is carried out to RAM
18
. In RAM
17
, the data write operation is carried out in directions shown by FIG.
6
A and at the same time, the data read operation is carried out in directions shown by FIG.
6
B. The write address forming circuit
14
and the read address forming circuit
15
are operated in synchronism with each other by the write/read switching signal
201
and therefore, the write operation and the read operation of RAM
17
and RAM
18
are simultaneously started and finished. Further, successively, the data read operation is carried out in RAM
17
in the directions shown by FIG.
6
B and the data write operation is carried out in RAM
18
in the directions shown by FIG.
6
A.
By the above-described operation, the time-sequential order of the input data Din inputted from the data input terminal
11
is converted and the input data Din is outputted from a data output terminal
20
as output data Dout.
In this way, two storages (RAM
17
,
18
) are needed in the conventional interleave circuit and the read write address switching control and the data read write switching control are needed in RAMs
17
and
18
. Further, when the data speed is accelerated, high speed RAM is needed to cause an increase in the cost in realizing the circuit.
Further, when data is dealt with by a symbol unit in which 1 symbol is constituted by m bits, although time-sequential conversion of symbol can be realized by the above-described method, in the time-sequential conversion of bits constituting symbols, there are needed a write address forming circuit, a read address forming circuit and two pieces of storages (RAM) for each bit, the circuit scale is magnified and the cost is also increased.
According to the above-described conventional block interleave circuit, interleaving of input data is carried out by using the storages and therefore, there poses a problem in which when data speed is accelerated, high-speed storages are needed and when an amount of data to be converted is increased, a necessary memory amount is increased and therefore, the cost is increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a block interleave circuit capable of carrying out time-sequential conversion of data with no need of complicated control even when data speed is high.
In order to achieve the above-described object, according to an aspect of the present invention, there is provided a block interleave circuit for segmenting a constant amount of data in input data into one block and converting a time-sequential order of data in the block, the block interleave circuit comprising:
serial/parallel conversion means for converting the constant amount of the data in the input data into parallel signals; and
parallel/serial conversion means for converting the time-sequential order by inputting the parallel signals generated by the serial/parallel conversion means in a previously set order and successively shifting the parallel signals.
Further, according to another aspect of the present invention, the serial/parallel conversion means comprises:
a frequency dividing circuit for dividing an input clock by using frame signals which are signals indicating segmentation of the block of the input data and outputting a divided clock;
a first shift register comprising data flip flop circuits connected in a vertical column and having a number in correspondence with the constant amount of the data for shifting the input data bit by bit by using the input clock to thereby output a constant amount of data in the input data as parallel data; and
a register comprising data flip flop circuits having a number in accordance with the constant amount of data for respectively latching a constant amount of the parallel data outputted from the first shift register by the divided clock from the frequency dividing circuit.
Further, according to another aspect of the present invention, the parallel/serial conversion means comprises:
a data load signal generating circuit for generating a data load signal outputted at a timing at which all of one block of data has been read by delaying the divided clock by one clock by the input clock; and
a second shift register comprising:
data flip flop circuits connected in vertical columns and having a number in accordance with the constant amount of data; and
a plurality of logical circuits for parallelly loading a constant amount of data latched by the serial/parallel conversion me

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