Method for forming a shallow trench isolation structure

Details Method for forming a shallow trench isolation structure Method for forming a shallow trench isolation structure

1999-09-15

2002-02-05

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S690000, C438S691000, C438S700000

Reexamination Certificate

active

06344415

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming shallow trench isolation (STI) structures.
2. Description of the Related Art
Advances in the production of integrated circuits have led to an increase in the level of integration and the miniaturization of semiconductor devices. As the level of integration increases, both the dimensions of each device and size of the isolating structures between devices are reduced. Consequently, device isolation structures are increasingly harder to form. A device isolation structure such as a field oxide layer formed by local oxidation (LOCOS) is no longer suitable for small dimensional devices due to the intensification of bird's beak encroachment problem. Therefore, the shallow trench isolation (STI) method has been developed for highly integrated circuits, and, in particular, sub-half micron integrated circuits.
In general, a shallow trench isolation (STI) structure is formed by performing an anisotropic etching operation using a silicon nitride hard mask to form a steep-sided trench in a semiconductor substrate. Oxide material is next deposited into the trench to form an oxide plug. However, the aforementioned method of STI fabrication often results in the formation of recess cavities around the edge region of the oxide plug. The recess cavities often produce what is called a corner effect. For example, after the polysilicon gate is formed, the gate electrode field is partially increased. Often, this leads to an abnormal flow of subthreshold current in the transistor channel resulting in the intensification of kink effect. Hence, the transistor can no longer operate normally and reliably. Moreover, polysilicon stringers may form in the cavities causing unwanted connections and side effects.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method for forming a shallow trench isolation (STI) structure capable of preventing the formation of recess cavities around the corner area of the active region.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a STI structure. A pad oxide layer is formed over a substrate. An amorphous silicon layer is formed over the pad oxide layer. A mask layer is formed over the amorphous silicon layer. The mask layer is patterned, and then the amorphous silicon layer, the pad oxide layer and the substrate are etched in sequence to form a trench. A thermal oxidation is carried out to form a liner layer along the exposed sidewalls of the amorphous silicon layer and the exposed substrate surface inside the trench. Insulation material is deposited over the substrate, completely filling the trench. A chemical-mechanical polishing step is carried out to remove a portion of the insulation layer and a portion of the mask layer so that an insulation plug is formed inside the trench. After the polishing step, the top surface of the insulation plug and the top surface of the mask layer are at the same surface. The mask layer is patterned to expose a portion of the amorphous silicon layer near the central region of two neighboring trenches. An ion implantation is carried out. The mask layer is removed. The amorphous silicon layer is removed.
The invention also provides an alternative method for forming a STI structure. A pad oxide layer, an amorphous silicon layer and a mask layer are sequentially formed over a substrate. The mask layer is patterned, and then the amorphous silicon layer, the pad oxide layer and the substrate are etched in sequence to form a trench. A thermal oxidation is carried out to form a liner layer along the exposed sidewalls of the amorphous silicon layer and the exposed substrate inside the trench. Insulation material is deposited over the substrate, completely filling the trench. A planarization step that retains a portion of the mask layer is carried out. The mask layer is patterned to expose a portion of the amorphous silicon layer near the central region of two neighboring trenches. An ion implantation is carried out. Finally, etching is carried out to remove the mask layer and the amorphous silicon layer above the pad oxide layer as well as a top layer of the insulation plug and the liner oxide layer in the active region.
Since etching selectivity between the amorphous silicon layer and the pad oxide layer is high, the pad oxide layer can serve as an etching stop layer for removing the mask layer and the amorphous silicon layer. The mask layer thus is completely removed without residue. A cop corner taper angle can be well controlled. Moreover, the amorphous silicon layer is formed between the mask layer and the pad oxide and while forming the pad oxide layer, the sidewall portion of the amorphous silicon layer is oxidized to form the sidewall oxide layer. The amorphous silicon layer and the sidewall oxide layer are able to protect the corner area of the active region when the mask layer is etched without exposing the corner area of the active region. In addition, the ion implantation is only performed on the device channel region, the capacity and electric field of the junction region of the source/drain region are decreased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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