Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2000-08-28
2002-06-25
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C377S047000
Reexamination Certificate
active
06411669
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a dual-modulus prescaler for a RF frequency synthesizer, and more particularly to a dual-modulus prescaler for a RF frequency synthesizer, which may operate in a high speed and reduce energy consumption.
2. Description of the Prior Art
Generally, a radio frequency (RF) synthesizer means a phase locked loop (hereinafter, referred as PLL), which outputs wider-ranged frequency by adjusting values of a programmable counter and is applied mainly to communication systems such as a portable personal mobile communication, an amateur communication, airplane, and so on.
FIG. 1
is a block diagram showing a receiver in the general portable personal mobile communication. As shown in the figure, the receiver includes a low-noise amplifier
10
for linearly amplifying at a predetermined ratio a signal received from a public network through an antenna
1
, a variable frequency synthesizer
20
for generating an oscillation signal with a variable frequency, a first mixer
40
for generating a signal with a middle frequency by mixing a frequency of the signal amplified in the low-noise amplifier
10
and a frequency of the output signal of the variable frequency synthesizer
20
, a middle frequency amplifier
60
for amplifying the signal with the middle frequency at a predetermined ratio and outputting the amplified signal, a fixed frequency synthesizer
80
for first and second oscillation signals with fixed frequencies, a second mixer
100
for outputting first and second mixed signals by mixing a frequency of the signal amplified in the middle frequency amplifier
60
and a frequency of the signal from the fixed frequency synthesizer
80
, a low-pass filter
120
for filtering to pass a low frequency bandwidth of the first and second mixed signals, and an analog-digital (AD) converter
140
for converting an analog signal filtered in the low-pass filter
120
to a digital signal and outputting a baseband signal (BBS).
FIG. 2
is a block diagram for illustrating the general frequency synthesizer
20
. As shown in the figure, the frequency synthesizer
20
includes a phase detector
21
for detecting phases of a reference frequency F
r
and a feedback input frequency to generate an error signal voltage, a charge pump
22
for pumping a charge according to the error signal voltage, a loop filter
24
for integrating outputs of the charge pump
22
and controlling a PLL loop gain, a voltage controlled oscillator (VCO)
26
for outputting, as a clock signal CLK, a signal in an oscillation frequency F
o
controlled in response to an error signal voltage, which eliminates noise from the loop filter
24
, and a programmable frequency divider
28
outputting a frequency signal divided at a predetermined ratio in response to the clock signal CLK from the VCO
26
and feeding back the divided frequency signal as an input of the phase detector
21
.
The programmable frequency divider
28
includes a dual-modulus prescaler
28
a
for dividing the clock signal CLK from the VCO in first and second modes with different dividing ratios in response to a feedback counting signal (MC) and outputting the divided clock signal CLK, a first counter
28
b
for counting clock pulses divided in the dual-modulus prescaler
28
a
to output the count as an input frequency signal of the phase detector
21
, and a second counter
28
c
for counting clock pulses divided in the dual-modulus prescaler
28
a
and outputting a mode control signal (MC) according to the count to the dual-modulus prescaler
28
a.
The frequency synthesizer
20
has a configuration that the loop filter
24
and the VCO are attached to outside of a PLL module having the phase detector
21
, the charge pump
22
and the programmable frequency divider
28
.
In the frequency synthesizer constructed as above, the output frequency F
o
becomes a value multiplying the reference frequency F
r
by a total dividing ratio (M) which is divided by the programmable frequency divider
28
.
Such RF variable frequency synthesizer using a Pulse Swallow Method includes the programmable frequency divider
28
in which a total dividing ratio is M and which is composed of three elements: the dual-modulus prescaler
28
a
and the first and second counters
28
b
,
28
c
. At this time, the output frequency F
o
of each element is determined by combinations of programmed counts of the elements.
Provided that a dividing ratio of the dual-modulus prescaler
28
a
is P and counts of the first and second counters
28
b
,
28
c
are respectively N and S, the output frequency F
o
is calculated as follows.
F
o
=
M_F
r
=
(
P_N
+
S
)
F
r
Equation
1
where,
P=2
n
, (n=
1, 2, - - - )
S=0~(P−1)
N≧S.
The dual-modulus prescaler
28
a
at first divides the CLK frequency of the VCO
26
in the first and second modes having different dividing rates, for example P and P+1. In fact that the VCO
26
operates in the highest frequency in the frequency synthesizer, the dual-modulus prescaler
28
a
also requires high speed operation.
Such high speed operation consumes much energy and the prescaler
28
a
occupies most of the power consumed in the PPL module.
Therefore, the high speed operation and low energy consumption of the prescaler
28
a
is needed to the RF synthesizer for the mobile communications.
The prescaler
28
a
currently used is implemented in a shift register ring method.
FIG. 3
is a block diagram showing the conventional prescaler
28
a
employing the shift register ring method. As shown in the figure, the prescaler
28
a
includes a high speed synchronous divider
28
a
-
1
operating at a 4/5 dividing rate, a low speed asynchronous divider
28
a
-
2
operating at a 32 dividing rate, and a logic gate
28
a
-
3
.
The synchronous divider
28
a
-
1
includes first to third flip-flops FF
1
-FF
3
which is synchronous with the CLK of the VCO
26
, an inverter INV for inverting an output of the first flip-flop, a first NAND gate (ND
1
) for inverted-AND operating an output signal of the inverter INV and an inputted control signal CTR and outputting the operated signal as an input of the second flip-flop FF
2
, and a second NAND gate (ND
2
) for inverted-AND operating the output signals of the first and second flip-flops FF
1
, FF
2
and outputs the operated signals as inputs of the third flip-flop FF
3
.
The output signal of the third flip-flop FF
3
is fed back as an input of the first flip-flop FF
1
as well as used as a synchronous signal of the asynchronous divider
28
a
-
2
.
The asynchronous divider
28
a
-
2
includes five two-dividing flip-flops (FF
4
-FF
8
) for supplying an output Q as a synchronous signal of the next flip-flop and feeding back an inverse output /Q as an input thereof. The fourth flip-flop FF
4
is synchronous with an output signal of the third flip-flop FF
3
.
The logic gate
28
a
-
3
includes an AND gate for AND operating output signals of the two-dividing flip-flops FF
4
-FF
8
and a mode control signal MC from the second counter
28
c.
Operation of the dual-modulus prescaler
28
a
employing the shift register ring method and constructed is explained below with reference to a timing diagram in FIG.
4
.
The dual-modulus prescaler
28
a
selects a dividing rate according to a logic level of the mode control signal MC, which can be P or P+1. In other words, the dividing ratio is P when the mode control signal MC is a logic level “low”, or else the dividing ratio is P+1.
At first, a dividing operation at P(=2
7
=128) is same as a ripple counter. That is, because the AND gate of the decoder
28
a
-
3
always outputs low when the mode control signal MC is selected as a logic level “low”, the control signal CTR become a logic level “low”. If the signal is inputted to the first and second ANAD gates ND
1
, ND
2
of the synchronous divider
28
a
-
1
, the NAND gates output a logic level “high”. As a result, the synchronous divider
28
a
-
1
becomes a four-divider having two flip-flops and an i
Bacon & Thomas
C&S Technology Co., Ltd.
Wambach Margaret R.
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