Static information storage and retrieval – Powering
Reexamination Certificate
2001-05-18
2002-08-06
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Powering
C365S225700, C365S200000
Reexamination Certificate
active
06430102
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No.
2000-198099
, filed on Jun. 30, 2000, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits and methods for controlling activation thereof, in particular, suitable for use in a redundancy judgment circuit for determining redundancy of a redundant circuit upon activation.
2. Description of the Related Art
In order to lower electric power consumption, conventionally, an integrated circuit of a memory or the like has been required to lower the operational voltage. In recent years, for example, in a DRAM (Dynamic Random Access Memory), there is an integrated circuit that operates with an inner power supply voltage of about 2.0 V and a negative voltage of about −0.5 V.
A redundant circuit has been provided in the integrated circuit of a memory or the like in advance to remedy failure due to defect in the integrated circuit. In the case that failure has occurred in a portion of the circuit, the circuit that the failure occurs has been replaced with a redundant circuit to remedy the failure. In this integrated circuit provided with the redundant circuit, a fuse or the like to select whether the redundant circuit should be used or not is disposed and to replace the circuit, in which failure has occurred, with the redundant circuit is selected depending on whether the fuse or the like should be cut or not. In this case, when the integrated circuit is used in a normal operation, it is judged by a redundancy judgment circuit upon activation whether the integrated circuit lies in the condition of using the redundant circuit or not.
FIG. 1
is a diagram for showing a constitutional example of a redundancy judgment circuit, which is used in a conventional memory or the like.
In
FIG. 1
, a reference numeral
1
denotes a starter signal generation circuit for generating and outputting a starter signal STT in order to determine an initial state of a peripheral circuit. This starter signal STT rises together with a power supply voltage Vii when the power supply is turned on and it is reset at a low level when the potential of the power supply voltage Vii reaches a predetermined potential Vb.
A reference numeral
2
′ denotes a negative voltage generation circuit, which generates a negative voltage Vnn to be used in the integrated circuit including the redundancy judgment circuit. The negative voltage Vnn generated by the negative voltage generation circuit
2
′ is supplied to a starter signal level shifter
3
, a fuse set pulse generation circuit
4
and a fuse information latch circuit
5
or the like.
The starter signal level shifter
3
shifts a low level of the starter signal STT, which is supplied from the starter signal generation circuit
1
, from a ground potential Vss to a potential of the negative voltage Vnn. The starter signal level shifter
3
supplies a signal, which shows that the low level is shifted to the potential of the negative voltage Vnn, to the fuse set pulse generation circuit
4
and the fuse information latch circuit
5
as a fuse starter signal STTB.
The fuse set pulse generation circuit
4
comprises a circuit for generating a fuse set pulse signal FSETP to judge the redundancy on the basis of the supplied fuse starter signal STTB. Then, the fuse set pulse generation circuit
4
supplies the generated fuse set pulse signal FSETP to the fuse information latch circuit
5
.
The fuse information latch circuit
5
is provided with a fuse to select whether the redundant circuit should be used or not. The fuse information latch circuit
5
judges upon activation whether the fuse is cut or not and stores this judgment result therein. That is, the fuse information latch circuit
5
uses the generated fuse set pulse signal FSETP, which is supplied from the fuse set pulse generation circuit
4
, to judge upon activation whether the current fuse is cut or not and store this judgment result therein. The fuse information latch circuit
5
outputs the above judgment result through an output node
6
as an output signal FSZ.
The low level of each of the fuse set pulse signal FSETP and the output signal FSZ respectively output from the above described fuse set pulse generation circuit
4
and the above described fuse information latch circuit
5
is equal to the potential of the negative voltage Vnn.
FIG. 2
is a diagram for showing a configuration of a conventional negative voltage generation circuit
2
′.
In
FIG. 2
, a reference numeral
31
denotes a negative voltage judgment circuit. The negative voltage judgment circuit
31
judges whether the potential of the negative voltage Vnn to be output through an output node
34
of the negative voltage generation circuit
2
′ is lowered to a predetermined potential or not. Additionally, the negative voltage judgment circuit
31
outputs the judgment result to a negative voltage generation enable circuit
32
.
The negative voltage generation enable circuit
32
outputs an enable signal EN for controlling a negative voltage generation operation. This enable signal EN is generated on the basis of the judgment result to be supplied from the negative voltage judgment circuit
31
and a memory bank activation signal BRAS to be input through an input node
35
. Additionally, the memory bank activation signal BRAS comprises a signal such that ‘H’ is output upon activating the memory bank. However, it is clamped in ‘L’ by a not-shown circuit upon activation. Therefore, the negative voltage generation enable circuit
32
outputs the enable signal EN only on the basis of the judgment result to be supplied from the negative voltage judgment circuit
31
upon activation.
A reference numeral
33
denotes an oscillation and pumping circuit. The oscillation and pumping circuit
33
generates the negative voltage Vnn and outputs it through the output node
34
in accordance with the enable signal EN to be supplied from the negative voltage generation enable circuit
32
. The oscillation and pumping circuit
33
shown in
FIG. 2
performs the negative voltage generation operation when the enable signal EN is ‘H’ and it does not perform the negative voltage generation operation when the enable signal EN is ‘L’.
FIG. 3
is a timing chart for explaining the operation of a conventional redundancy judgment circuit.
In
FIG. 3
, the power supply voltage Vii rises up when the power supply is turned on at a time of T
10
. As the power supply voltage Vii rises up, the enable signal EN, the starter signal STT, the fuse starter signal STTB, the fuse set pulse signal FSETP and the output signal FSZ also rise up.
When the potential of the power supply voltage Vii reaches a predetermined potential Va at a time of T
11
, the oscillation and pumping circuit
33
in the negative voltage generation circuit
2
′ detects that the enable signal EN is ‘H’. This allows the negative voltage generation operation to be started by the oscillation and pumping circuit
33
and the potential of the negative voltage Vnn to be output from the negative voltage generation circuit
2
′ is lowered. Then, the oscillation and pumping circuit
33
continues the negative voltage generation operation until a time of T
12
, when the potential of the negative voltage Vnn reaches a predetermined potential.
When the negative voltage judgment circuit
31
judges that the potential of the negative voltage Vnn reaches a predetermined potential at a time of T
12
, the negative voltage judgment circuit
31
outputs this judgment result to the negative voltage generation enable circuit
32
. Depending on this judgment result, the negative voltage generation enable circuit
32
makes the enable signal EN at ‘L’. Thus, the negative voltage generation operation of the oscillation and pumping circuit
33
is not performed and the negative voltage Vnn to be output from the negative voltage generation circuit
2
′ bec
Matsumiya Masato
Mori Kaoru
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nguyen Tan T.
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