Internal offset-canceled phase locked loop-based deskew buffer

Details Internal offset-canceled phase locked loop-based deskew buffer Internal offset-canceled phase locked loop-based deskew buffer

2001-01-05

2002-02-12

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06346838

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to a deskew buffer having a delay-locked loop.
2. Background Information
The phase-locked loop (PLL) circuit is widely used in integrated circuit design. The PLL is used in applications such as clock generators, clocks/data recovery, deskew buffers, and frequency synthesizers.
For synchronous systems, the skew (e.g., phase offset or time difference) between input and feedback clocks signals degrades the timing budget of the synchronous operation. In a high-speed digital application, the PLL often serves as the on-chip clock generator or deskew buffer to synchronize with the external system frequency and to minimize skew. A delay-locked loop (DLL) circuit is often used to aid in the deskew application. The main difference between a PLL and a DLL in the deskew application is that the PLL can provide different frequencies via divider ratios, while the DLL can provide only a fixed frequency in most cases.
A prior art PLL-based deskew buffer circuit
10
is shown in FIG.
1
. The main goal of the PLL-based deskew buffer is to align the phases of the input clock CLK_IN and feedback clock CLK_FB. The circuit
10
includes a reference divider
12
to receive an input clock signal CLK_IN and to output a reference signal REF. The reference signal REF forms a first input into a phase/frequency detector (PFD)
26
. At the other end of the circuit
10
, a clock tree unit
14
receives an output clock signal CLK_OUT from a voltage-controlled oscillator (VCO)
24
and outputs a feedback clock signal CLK_FB. The feedback clock signal CLK_FB is fed into a feedback divider
16
, which in turn outputs a signal FB. The signal FB forms a second input into the PFD
26
.
When the PLL is in-lock to provide the desired PLL output frequency, the skew (e.g., internal phase/time offset) between the input clock signal CLK_IN and the feedback clock signal CLK_FB that comes from the PLL might still exist. In other words, while the frequency of the feedback clock signal CLK_FB may be exactly locked to a multiple of the frequency of the input clock signal CLK_IN, their phases, however, may be only “approximately” locked. Internal components in the circuit
10
contribute to this slight offset or skew in their phases.
The amount of this skew depends on the type of circuit component selected, such as a charge pump
20
, loop filter
22
, and VCO
24
. For fixed-frequency operation, the offset might be determined and avoided in advance. For example, one only needs to add some predetermined fixed delay in the signal paths to cancel their skew. For wide-frequency range operation of the PLL (e.g., where the PLL may be required during operation to adjust to different frequencies over a wide range), the control voltage V
c
of the VCO
24
derived from the charge pump
20
and the loop filter
22
will vary as the PLL adjusts to different frequencies. The charge injection amount caused from switches (not shown) of the charge pump
20
will be different for different control voltages V
c
. This may severely affect the phase performance of the PLL. It means that, at different control voltages V
c
(at the loop filter's
22
output), the voltage difference will also be different even though the input clock signal CLK_IN and feedback clock signal CLK_FB may be in phase for one of the control voltages V
c
.
FIG. 2
helps to further illustrate this problem. First, most of the frequently used PFDs
26
generate both up (UP) and down (DN) pulses to avoid a dead zone. At different operating frequencies (e.g., at different control voltages V
C1
, V
C2
, V
C3
of the VCO
24
), the curves of the phase difference &PHgr; between the input clock signal CLK_IN and the feedback clock signal CLK_FB versus voltage change V are shown in
FIG. 2
, where V represents a change in the control voltage V
c
. Many PLLs will have an ideal control voltage V
c2
, where the input clock signal CLK_IN and feedback clock signal CLK_FB are in phase.
However, under certain situations when the control voltage V
c
changes from the ideal control voltage V
c2
, to other control voltages, the net charge injected into the loop filter
22
(comprising of a resistor and capacitors) is not zero even though the input clock signal CLK_IN and feedback clock signal CLK_FB are in phase. In other words, the phenomenon means that an internal offset exists between the input clock signal CLK_IN and the feedback clock signal CLK_FB when the PLL output frequency is locked.
For example in
FIG. 2
, if the control voltage V
c
of the VCO
24
is operating at a control voltage V
c1
, to provide an in-lock frequency, then t
o1
, is a phase/time offset between the input clock signal CLK_IN and the feedback clock signal CLK_FB. That is, the phase offset t
o1
, between these two signals at the control voltage V
c1
is represented by the phase/time difference between the V
c1
and V
c2
curves caused by charge injection.
As discussed, this phase/time offset can degrade performance. Therefore, what is needed is an improved deskew buffer.


REFERENCES:
patent: 5371764 (1994-12-01), Gillingham et al.
patent: 5594376 (1997-01-01), McBride et al.
patent: 5642082 (1997-06-01), Jefferson
patent: 6127866 (2000-10-01), Chu et al.
patent: 6208183 (2001-03-01), Li et al.

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