Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-07-05
2002-11-26
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06487121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a method of programming multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomena of hot electron injection to trap charge within a trapping dielectric material within the gate.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can l e programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programed by hot electron injection and the injected charges are stored in the oxide-nitride-oxide (ONO) layer of the device. This article teaches programming and reading in the forward direction. Thus, a wider charge trapping region is required to achieve a sufficiently large difference in threshold voltages between programmed and erase id states, and only one physical location per cell is used to store the electrons.
An attempt to improve the programming of such ONO EEPROM devices by using two distinct locations per cell to store the electrons is disclosed in both U.S. Pat. No. 5,768,192 and PCT patent application publication WO 99/07000, the contents of which are hereby incorporated herein by reference. In those disclosed devices, a cell is programmed using hot electron programming, each bit is read in a direction opposite that in which it was programmed with a relatively low gate voltage. For example, the right bit is programmed conventionally by applying programming or voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into a region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. The left bit is similarly programmed and read by swapping the functionality of source and drain terminals. Programming one the bits leaves the other bit with its information intact and undisturbed. Programming one of the bits, however, have a very small effect on the other bit, e.g., slightly slower programming speed for the second bit. However, the efficiency of such programming is often inadequate since most of the hot electrons are placed too near the drain. In addition, injection of the electrons into the gate is done by giving the electrons enough energy to surmount the oxide barrier. However, the energy is supplied solely from a lateral electric field that produces energetic electrons in the drain.
SUMMARY OF THE INVENTION
One aspect of the present invention regards a method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method further includes applying a lateral electric field within the channel that generates a depletion layer that has electrons at a bottom portion of the depletion layer and applying a vertical electric field within the channel that has a sufficient strength so that the electrons at the bottom portion of the depletion layer are injected into the charge trapping region.
The above aspect of the present invention provides the advantage of improving the efficiency of programming by more efficiently imparting the energy necessary for injecting electrons in the gate oxide.
The above aspect of the present invention provide the advantage of more effectively controlling the injection location to make erasing more complete.
The above aspect of the present invention provides the advantage of improving the endurance (cycling) of a memory cell.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.
REFERENCES:
patent: 6030871 (2000-02-01), Eitan
patent: 6044022 (2000-03-01), Nachumovsky
patent: 6348711 (2002-02-01), Eitan
Huster Carl R.
Thurgate Timothy J.
Amin & Turocy LLP
Ho Hoai
Nguyen Thinh
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