System for radial clock distribution and skew regulation for syn

Details System for radial clock distribution and skew regulation for syn System for radial clock distribution and skew regulation for syn

1992-04-24

1995-06-27

Lall, Parshotam S.

Excavating

371 1, 307409, 375356, 327258, 327292, H03K 5135, H03K 514

Patent

active

054287642

ABSTRACT:
A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines. The output of the interval driver circuitry is input to local buffer circuitry that distributes the converted clocking signals to elements of a component for use as clocking signals.

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